From 4de127a44a45a8135756d4a7f26919393b91bb32 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 23 Oct 2024 08:09:23 +0200 Subject: [PATCH 01/16] arm64: zynqmp: Configure SoC RTC on SOM Use RTC available in HW on Kria SOM without using emulation that's why configure it properly and disable emulated one. Power on reset value of RTC Calibration register without battery backup is not matching with crystal frequency which leads to RTC time drift. That's why write CALIB_WRITE register with crystal frequency (0x7FFF). There is also an option to write zero so that Linux will set default value (0x7FFF) in driver probe but calibration 0 is not permited by DT schema. Co-developed-by: Srinivas Goud Signed-off-by: Srinivas Goud Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/9b684faeec85381b9b8fe796aaebc2ee79f17b8e.1729663761.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-sm-k26-revA.dts | 1 + configs/xilinx_zynqmp_kria_defconfig | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts index 8056f6b176e..8c43ade9405 100644 --- a/arch/arm/dts/zynqmp-sm-k26-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts @@ -387,6 +387,7 @@ &rtc { status = "okay"; + calibration = <0x7fff>; }; &lpd_dma_chan1 { diff --git a/configs/xilinx_zynqmp_kria_defconfig b/configs/xilinx_zynqmp_kria_defconfig index dd4df0b2da1..0dddf69c5d0 100644 --- a/configs/xilinx_zynqmp_kria_defconfig +++ b/configs/xilinx_zynqmp_kria_defconfig @@ -187,7 +187,6 @@ CONFIG_DM_PWM=y CONFIG_PWM_CADENCE_TTC=y CONFIG_RESET_ZYNQMP=y CONFIG_DM_RTC=y -CONFIG_RTC_EMULATION=y CONFIG_RTC_ZYNQMP=y CONFIG_SCSI=y CONFIG_ARM_DCC=y From 7aeed221dbd354f34428d709dfd7679a2c94199d Mon Sep 17 00:00:00 2001 From: Saeed Nowshadi Date: Thu, 24 Oct 2024 12:42:33 +0200 Subject: [PATCH 02/16] arm64: zynqmp: Fix pwm-fan polarity In previous version of pwm driver, the polarity of pwm were implemented in reverse. In recent release, that issue in the driver is fixed, therefore, correctly set the polarity in the device tree. Signed-off-by: Saeed Nowshadi Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/3e8e38b77101335f86bca0f05b3988877bb12993.1729766551.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-sc-revB.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/zynqmp-sc-revB.dts b/arch/arm/dts/zynqmp-sc-revB.dts index 1af3f643567..c4f70581695 100644 --- a/arch/arm/dts/zynqmp-sc-revB.dts +++ b/arch/arm/dts/zynqmp-sc-revB.dts @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP Generic System Controller * * (C) Copyright 2021 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2024, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -80,7 +80,7 @@ pwm-fan { compatible = "pwm-fan"; status = "okay"; - pwms = <&ttc0 2 40000 1>; + pwms = <&ttc0 2 40000 0>; }; }; From feb423a3a3d34ed7903d6eb833ddd0593a410474 Mon Sep 17 00:00:00 2001 From: Sughosh Ganu Date: Fri, 25 Oct 2024 22:57:23 +0530 Subject: [PATCH 03/16] common: memtop: add logic to detect ram_top Add generic logic to determine the ram_top value for boards. Earlier, this was achieved in an indirect manner through a set of LMB API's. That has since changed so that the LMB code is available only after relocation. Replace those LMB calls with a single call to get_mem_top() to determine the value of ram_top. Signed-off-by: Sughosh Ganu Reviewed-by: Michal Simek Link: https://lore.kernel.org/r/20241025172724.195093-2-sughosh.ganu@linaro.org Signed-off-by: Michal Simek --- common/Makefile | 1 + common/memtop.c | 171 +++++++++++++++++++++++++++++++++++++++++++++++ include/memtop.h | 22 ++++++ 3 files changed, 194 insertions(+) create mode 100644 common/memtop.c create mode 100644 include/memtop.h diff --git a/common/Makefile b/common/Makefile index 2ee5ef9cc6e..35991562a12 100644 --- a/common/Makefile +++ b/common/Makefile @@ -7,6 +7,7 @@ ifndef CONFIG_XPL_BUILD obj-y += init/ obj-y += main.o +obj-y += memtop.o obj-y += exports.o obj-y += cli_getch.o cli_simple.o cli_readline.o obj-$(CONFIG_HUSH_OLD_PARSER) += cli_hush.o diff --git a/common/memtop.c b/common/memtop.c new file mode 100644 index 00000000000..841d89e0799 --- /dev/null +++ b/common/memtop.c @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2024, Linaro Limited + */ + +#include +#include +#include + +#include + +#define MEM_RGN_COUNT 16 + +struct region { + phys_addr_t base; + phys_size_t size; +}; + +struct mem_region { + struct region rgn[MEM_RGN_COUNT]; + uint count; +}; + +static void add_mem_region(struct mem_region *mem_rgn, phys_addr_t base, + phys_size_t size) +{ + long i; + + for (i = mem_rgn->count; i >= 0; i--) { + if (i && base < mem_rgn->rgn[i - 1].base) { + mem_rgn->rgn[i] = mem_rgn->rgn[i - 1]; + } else { + mem_rgn->rgn[i].base = base; + mem_rgn->rgn[i].size = size; + break; + } + } + + mem_rgn->count++; +} + +static void mem_regions_init(struct mem_region *mem) +{ + uint i; + + mem->count = 0; + for (i = 0; i < MEM_RGN_COUNT; i++) { + mem->rgn[i].base = 0; + mem->rgn[i].size = 0; + } +} + +static int fdt_add_reserved_regions(struct mem_region *free_mem, + struct mem_region *reserved_mem, + void *fdt_blob) +{ + u64 addr, size; + int i, total, ret; + int nodeoffset, subnode; + struct fdt_resource res; + + if (fdt_check_header(fdt_blob) != 0) + return -1; + + /* process memreserve sections */ + total = fdt_num_mem_rsv(fdt_blob); + assert_noisy(total < MEM_RGN_COUNT); + for (i = 0; i < total; i++) { + if (fdt_get_mem_rsv(fdt_blob, i, &addr, &size) != 0) + continue; + add_mem_region(reserved_mem, addr, size); + } + + i = 0; + /* process reserved-memory */ + nodeoffset = fdt_subnode_offset(fdt_blob, 0, "reserved-memory"); + if (nodeoffset >= 0) { + subnode = fdt_first_subnode(fdt_blob, nodeoffset); + while (subnode >= 0) { + /* check if this subnode has a reg property */ + ret = fdt_get_resource(fdt_blob, subnode, "reg", 0, + &res); + if (!ret && fdtdec_get_is_enabled(fdt_blob, subnode)) { + addr = res.start; + size = res.end - res.start + 1; + assert_noisy(i < MEM_RGN_COUNT); + add_mem_region(reserved_mem, addr, size); + } + + subnode = fdt_next_subnode(fdt_blob, subnode); + ++i; + } + } + + return 0; +} + +static long addrs_overlap(phys_addr_t base1, phys_size_t size1, + phys_addr_t base2, phys_size_t size2) +{ + const phys_addr_t base1_end = base1 + size1 - 1; + const phys_addr_t base2_end = base2 + size2 - 1; + + return ((base1 <= base2_end) && (base2 <= base1_end)); +} + +static long region_overlap_check(struct mem_region *mem_rgn, phys_addr_t base, + phys_size_t size) +{ + unsigned long i; + struct region *rgn = mem_rgn->rgn; + + for (i = 0; i < mem_rgn->count; i++) { + phys_addr_t rgnbase = rgn[i].base; + phys_size_t rgnsize = rgn[i].size; + + if (addrs_overlap(base, size, rgnbase, rgnsize)) + break; + } + + return (i < mem_rgn->count) ? i : -1; +} + +static int find_ram_top(struct mem_region *free_mem, + struct mem_region *reserved_mem, phys_size_t size) +{ + long i, rgn; + phys_addr_t base = 0; + phys_addr_t res_base; + + for (i = free_mem->count - 1; i >= 0; i--) { + phys_addr_t rgnbase = free_mem->rgn[i].base; + phys_size_t rgnsize = free_mem->rgn[i].size; + + if (rgnsize < size) + continue; + + base = rgnbase + rgnsize - size; + while (base && rgnbase <= base) { + rgn = region_overlap_check(reserved_mem, base, size); + if (rgn < 0) + return base; + + res_base = reserved_mem->rgn[rgn].base; + if (res_base < size) + break; + base = res_base - size; + } + } + + return 0; +} + +phys_addr_t get_mem_top(phys_addr_t ram_start, phys_size_t ram_size, + phys_size_t size, void *fdt) +{ + int i; + struct mem_region free_mem; + struct mem_region reserved_mem; + + mem_regions_init(&free_mem); + mem_regions_init(&reserved_mem); + + add_mem_region(&free_mem, ram_start, ram_size); + + i = fdt_add_reserved_regions(&free_mem, &reserved_mem, fdt); + if (i < 0) + return 0; + + return find_ram_top(&free_mem, &reserved_mem, size); +} diff --git a/include/memtop.h b/include/memtop.h new file mode 100644 index 00000000000..28f62e24ea7 --- /dev/null +++ b/include/memtop.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2024, Linaro Limited + */ + +/** + * get_mem_top() - Compute the value of ram_top + * @ram_start: Start of RAM + * @ram_size: RAM size + * @size: Minimum RAM size requested + * @fdt: FDT blob + * + * The function computes the top address of RAM memory that can be + * used by U-Boot. This is being done by going through the list of + * reserved memory regions specified in the devicetree blob passed + * to the function. The logic used here is derived from the lmb + * allocation function. + * + * Return: address of ram top on success, 0 on failure + */ +phys_addr_t get_mem_top(phys_addr_t ram_start, phys_size_t ram_size, + phys_size_t size, void *fdt); From 62fbddf7c8e7e0226273392fe1f81b8358ebe3c9 Mon Sep 17 00:00:00 2001 From: Sughosh Ganu Date: Fri, 25 Oct 2024 22:57:24 +0530 Subject: [PATCH 04/16] xilinx: use get_mem_top() to compute ram_top Use the get_mem_top function to compute the value of ram_top. This was earlier done through LMB API's, which are no longer available till after relocation. Use get_mem_top() instead to compute the ram_top value. Signed-off-by: Sughosh Ganu Reviewed-by: Michal Simek Tested-by: Michal Simek Link: https://lore.kernel.org/r/20241025172724.195093-3-sughosh.ganu@linaro.org Signed-off-by: Michal Simek --- board/xilinx/common/board.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c index 38dd80533fa..e14ed2cff00 100644 --- a/board/xilinx/common/board.c +++ b/board/xilinx/common/board.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include "board.h" #include @@ -676,3 +677,27 @@ int ft_board_setup(void *blob, struct bd_info *bd) return 0; } #endif + +#ifndef MMU_SECTION_SIZE +#define MMU_SECTION_SIZE (1 * 1024 * 1024) +#endif + +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) +{ + phys_size_t size; + phys_addr_t reg; + + if (!total_size) + return gd->ram_top; + + if (!IS_ALIGNED((ulong)gd->fdt_blob, 0x8)) + panic("Not 64bit aligned DT location: %p\n", gd->fdt_blob); + + size = ALIGN(CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE); + reg = get_mem_top(gd->ram_base, gd->ram_size, size, + (void *)gd->fdt_blob); + if (!reg) + reg = gd->ram_top - size; + + return reg + size; +} From 6f7ff73fbae9dcf9fc86aaeb76599fcd9df937e9 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 1 Nov 2024 09:37:23 +0100 Subject: [PATCH 05/16] arm64: xilinx: Rename SPI_ADVANCE to SPI_STACKED_PARALLEL Align defconfigs with the latest Kconfig layout. Fixes: f896aa656774 ("mtd: spi-nor: Rename SPI_ADVANCE to SPI_STACKED_PARALLEL") Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/fe05a0e542d6117c10956e4a104123e46f956793.1730450241.git.michal.simek@amd.com --- configs/xilinx_versal_net_virt_defconfig | 2 +- configs/xilinx_versal_virt_defconfig | 2 +- configs/xilinx_zynq_virt_defconfig | 2 +- configs/xilinx_zynqmp_virt_defconfig | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/configs/xilinx_versal_net_virt_defconfig b/configs/xilinx_versal_net_virt_defconfig index 899776e9c7f..07afb9ddb99 100644 --- a/configs/xilinx_versal_net_virt_defconfig +++ b/configs/xilinx_versal_net_virt_defconfig @@ -128,12 +128,12 @@ CONFIG_XILINX_UARTLITE=y CONFIG_SOC_DEVICE=y CONFIG_SOC_XILINX_VERSAL_NET=y CONFIG_SPI=y -CONFIG_SPI_ADVANCE=y CONFIG_DM_SPI=y CONFIG_CADENCE_QSPI=y CONFIG_CADENCE_OSPI_VERSAL=y CONFIG_ZYNQ_SPI=y CONFIG_ZYNQMP_GQSPI=y +CONFIG_SPI_STACKED_PARALLEL=y CONFIG_TPM2_TIS_SPI=y CONFIG_USB=y CONFIG_DM_USB_GADGET=y diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index 32c6bcd2078..1a29c4aeff7 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -129,7 +129,6 @@ CONFIG_PL01X_SERIAL=y CONFIG_XILINX_UARTLITE=y CONFIG_SOC_XILINX_VERSAL=y CONFIG_SPI=y -CONFIG_SPI_ADVANCE=y CONFIG_DM_SPI=y CONFIG_CADENCE_QSPI=y CONFIG_HAS_CQSPI_REF_CLK=y @@ -137,6 +136,7 @@ CONFIG_CQSPI_REF_CLK=200000000 CONFIG_CADENCE_OSPI_VERSAL=y CONFIG_ZYNQ_SPI=y CONFIG_ZYNQMP_GQSPI=y +CONFIG_SPI_STACKED_PARALLEL=y CONFIG_TPM2_TIS_SPI=y CONFIG_USB=y CONFIG_DM_USB_GADGET=y diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig index eaaf105dd69..3b957874857 100644 --- a/configs/xilinx_zynq_virt_defconfig +++ b/configs/xilinx_zynq_virt_defconfig @@ -144,9 +144,9 @@ CONFIG_ZYNQ_GEM=y CONFIG_POWER_DOMAIN=y CONFIG_ARM_DCC=y CONFIG_ZYNQ_SERIAL=y -CONFIG_SPI_ADVANCE=y CONFIG_ZYNQ_SPI=y CONFIG_ZYNQ_QSPI=y +CONFIG_SPI_STACKED_PARALLEL=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_ULPI_VIEWPORT=y diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index ff8ab344595..7534cc32404 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -208,9 +208,9 @@ CONFIG_XILINX_UARTLITE=y CONFIG_ZYNQ_SERIAL=y CONFIG_SOC_XILINX_ZYNQMP=y CONFIG_SPI=y -CONFIG_SPI_ADVANCE=y CONFIG_ZYNQ_SPI=y CONFIG_ZYNQMP_GQSPI=y +CONFIG_SPI_STACKED_PARALLEL=y CONFIG_SYSRESET=y CONFIG_SYSRESET_CMD_POWEROFF=y CONFIG_SYSRESET_PSCI=y From b872583df10416d437ac18df6ad5c4095806c949 Mon Sep 17 00:00:00 2001 From: Padmarao Begari Date: Mon, 4 Nov 2024 17:57:50 +0530 Subject: [PATCH 06/16] arm64: zynqmp: Fix r5 mode for cpu release command The cpu release command for r5 mode (lockstep/split) argument accepts only string. But the zynqmp tcminit command accepts string or number for r5 mode (lockstep/split or 0/1) argument. To fix the r5 mode argument, the common argument (lockstep/split or 0/1) is used across different u-boot commands. Use the strcmp() instead of strncmp() to make uniform the r5 mode (lockstep/split or 0/1) for the zynqmp tcminit and cpu release command. Signed-off-by: Padmarao Begari Link: https://lore.kernel.org/r/20241104122750.96251-1-padmarao.begari@amd.com Signed-off-by: Michal Simek --- arch/arm/mach-zynqmp/mp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-zynqmp/mp.c b/arch/arm/mach-zynqmp/mp.c index 6e6da8008f4..448bc532867 100644 --- a/arch/arm/mach-zynqmp/mp.c +++ b/arch/arm/mach-zynqmp/mp.c @@ -352,7 +352,7 @@ int cpu_release(u32 nr, int argc, char *const argv[]) */ flush_dcache_all(); - if (!strncmp(argv[1], "lockstep", 8)) { + if (!strcmp(argv[1], "lockstep") || !strcmp(argv[1], "0")) { if (nr != ZYNQMP_CORE_RPU0) { printf("Lockstep mode should run on ZYNQMP_CORE_RPU0\n"); return 1; @@ -369,7 +369,7 @@ int cpu_release(u32 nr, int argc, char *const argv[]) dcache_enable(); set_r5_halt_mode(nr, RELEASE, LOCK); mark_r5_used(nr, LOCK); - } else if (!strncmp(argv[1], "split", 5)) { + } else if (!strcmp(argv[1], "split") || !strcmp(argv[1], "1")) { printf("R5 split mode\n"); set_r5_reset(nr, SPLIT); set_r5_tcm_mode(SPLIT); From cf3aa7b52ccfbd38540464507fbe17925b9ed3ff Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 25 Oct 2024 13:56:07 +0200 Subject: [PATCH 07/16] arm64: versal: Do not define do_reset() if sysreset is enabled If sysreset is enabled reset_cpu is defined in sysreset uclass that's why it can't be in platform/board code. The same change was done by commit f1bc214b0024 ("arm64: zynqmp: Do not define do_reset() if sysreset is enabled"). Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/8c1a5d6148c5e6c46790b725e8148a4e12d393ba.1729857366.git.michal.simek@amd.com --- board/xilinx/versal/board.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c index 39474674cca..27c1cfc6558 100644 --- a/board/xilinx/versal/board.c +++ b/board/xilinx/versal/board.c @@ -301,9 +301,11 @@ int dram_init(void) return 0; } +#if !CONFIG_IS_ENABLED(SYSRESET) void reset_cpu(void) { } +#endif #if defined(CONFIG_ENV_IS_NOWHERE) enum env_location env_get_location(enum env_operation op, int prio) From 064c8978b44fe0e3297e4fbf7a1e53479274372c Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 25 Oct 2024 13:56:08 +0200 Subject: [PATCH 08/16] arm64: versal: Enable capsule update (SD) Enable capsule update in SD boot mode. For getting it work there is a need to generate or setup dfu_alt_info and enable sysreset with DFU_MMC. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/cede513de764b99560dc3737457dbc8a5cc71d21.1729857366.git.michal.simek@amd.com --- board/xilinx/versal/board.c | 41 ++++++++++++++++++++++++++++ configs/xilinx_versal_virt_defconfig | 8 ++++++ 2 files changed, 49 insertions(+) diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c index 27c1cfc6558..fd5c6ced795 100644 --- a/board/xilinx/versal/board.c +++ b/board/xilinx/versal/board.c @@ -12,12 +12,15 @@ #include #include #include +#include +#include #include #include #include #include #include #include +#include #include #include #include @@ -338,3 +341,41 @@ enum env_location env_get_location(enum env_operation op, int prio) } } #endif + +#if defined(CONFIG_SET_DFU_ALT_INFO) + +#define DFU_ALT_BUF_LEN SZ_1K + +void set_dfu_alt_info(char *interface, char *devstr) +{ + int bootseq = 0, len = 0; + u32 bootmode = versal_get_bootmode(); + + ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN); + + if (env_get("dfu_alt_info")) + return; + + memset(buf, 0, sizeof(buf)); + + switch (bootmode) { + case EMMC_MODE: + case SD_MODE: + case SD1_LSHFT_MODE: + case SD_MODE1: + bootseq = mmc_get_env_dev(); + + len += snprintf(buf + len, DFU_ALT_BUF_LEN, "mmc %d=boot", + bootseq); + + len += snprintf(buf + len, DFU_ALT_BUF_LEN, ".bin fat %d 1", + bootseq); + break; + default: + return; + } + + env_set("dfu_alt_info", buf); + puts("DFU alt info setting: done\n"); +} +#endif diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index 1a29c4aeff7..3a4cd8f99f5 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -4,6 +4,7 @@ CONFIG_POSITION_INDEPENDENT=y CONFIG_SYS_INIT_SP_BSS_OFFSET=1572864 CONFIG_ARCH_VERSAL=y CONFIG_TEXT_BASE=0x8000000 +CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_SYS_MALLOC_F_LEN=0x100000 CONFIG_NR_DRAM_BANKS=36 CONFIG_SF_DEFAULT_SPEED=30000000 @@ -18,6 +19,10 @@ CONFIG_DEFINE_TCM_OCM_MMAP=y CONFIG_SYS_MEMTEST_START=0x00000000 CONFIG_SYS_MEMTEST_END=0x00001000 CONFIG_REMAKE_ELF=y +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_ON_DISK_EARLY=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y CONFIG_EFI_HTTP_BOOT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -76,6 +81,7 @@ CONFIG_TFTP_BLOCKSIZE=4096 CONFIG_SIMPLE_PM_BUS=y CONFIG_CLK_VERSAL=y CONFIG_DFU_TIMEOUT=y +CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1800000 CONFIG_ARM_FFA_TRANSPORT=y @@ -137,6 +143,8 @@ CONFIG_CADENCE_OSPI_VERSAL=y CONFIG_ZYNQ_SPI=y CONFIG_ZYNQMP_GQSPI=y CONFIG_SPI_STACKED_PARALLEL=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y CONFIG_TPM2_TIS_SPI=y CONFIG_USB=y CONFIG_DM_USB_GADGET=y From 4bd7222c6ba36715c5a4e1f6684bec63489e1acd Mon Sep 17 00:00:00 2001 From: Peter Korsgaard Date: Tue, 5 Nov 2024 17:21:36 +0100 Subject: [PATCH 09/16] boot/image-board.c: boot_get_fpga(): pass compatible flag to fpga_load() For E.G. signed FPGA bitstreams, similar to how it is done for the FPGA loading from SPL since commit 71f1a5392aad ("spl: fit: pass real compatible flags to fpga_load()"). Signed-off-by: Peter Korsgaard Link: https://lore.kernel.org/r/20241105162136.839633-1-peter@korsgaard.com Signed-off-by: Michal Simek --- boot/image-board.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/boot/image-board.c b/boot/image-board.c index 1757e5816d8..b726bd6b303 100644 --- a/boot/image-board.c +++ b/boot/image-board.c @@ -624,9 +624,10 @@ int boot_get_fpga(struct bootm_headers *images) void *buf; int conf_noffset; int fit_img_result; - const char *uname, *name; + const char *uname, *name, *compatible; int err; int devnum = 0; /* TODO support multi fpga platforms */ + int flags = 0; if (!IS_ENABLED(CONFIG_FPGA)) return -ENOSYS; @@ -674,20 +675,29 @@ int boot_get_fpga(struct bootm_headers *images) return fit_img_result; } + conf_noffset = fit_image_get_node(buf, uname); + compatible = fdt_getprop(buf, conf_noffset, "compatible", NULL); + if (!compatible) { + printf("'fpga' image without 'compatible' property\n"); + } else { + if (CONFIG_IS_ENABLED(FPGA_LOAD_SECURE)) + flags = fpga_compatible2flag(devnum, compatible); + } + if (!fpga_is_partial_data(devnum, img_len)) { name = "full"; err = fpga_loadbitstream(devnum, (char *)img_data, img_len, BIT_FULL); if (err) err = fpga_load(devnum, (const void *)img_data, - img_len, BIT_FULL, 0); + img_len, BIT_FULL, flags); } else { name = "partial"; err = fpga_loadbitstream(devnum, (char *)img_data, img_len, BIT_PARTIAL); if (err) err = fpga_load(devnum, (const void *)img_data, - img_len, BIT_PARTIAL, 0); + img_len, BIT_PARTIAL, flags); } if (err) From 159dfef2615dcc83acf4e28bbed0387d72066b0c Mon Sep 17 00:00:00 2001 From: Vasileios Amoiridis Date: Tue, 5 Nov 2024 14:27:44 +0100 Subject: [PATCH 10/16] drivers: bootcount: Add ZynqMP specific bootcount support Add native support of the bootcount mechanism in the ZynqMP by utilising internal PMU registers. The Persistent Global Storage Registers of the Platform Management Unit can keep their value during reboot cycles unless there is a POR reset, making them appropriate for the bootcount mechanism. Signed-off-by: Vasileios Amoiridis Reviewed-by: Heiko Schocher Link: https://lore.kernel.org/r/20241105132744.1572759-2-vassilisamir@gmail.com Signed-off-by: Michal Simek --- MAINTAINERS | 1 + arch/arm/mach-zynqmp/include/mach/hardware.h | 2 + drivers/bootcount/Kconfig | 7 +++ drivers/bootcount/Makefile | 1 + drivers/bootcount/bootcount_zynqmp.c | 47 ++++++++++++++++++++ 5 files changed, 58 insertions(+) create mode 100644 drivers/bootcount/bootcount_zynqmp.c diff --git a/MAINTAINERS b/MAINTAINERS index 0399ed1dbf6..bc27a514e86 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -860,6 +860,7 @@ M: Michal Simek S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git F: arch/arm/mach-zynqmp/ +F: drivers/bootcount/bootcount_zynqmp.c F: drivers/clk/clk_zynqmp.c F: driver/firmware/firmware-zynqmp.c F: drivers/fpga/zynqpl.c diff --git a/arch/arm/mach-zynqmp/include/mach/hardware.h b/arch/arm/mach-zynqmp/include/mach/hardware.h index 49e449ebd61..3c372bd6dcf 100644 --- a/arch/arm/mach-zynqmp/include/mach/hardware.h +++ b/arch/arm/mach-zynqmp/include/mach/hardware.h @@ -188,6 +188,8 @@ struct pmu_regs { u32 gen_storage4; /* 0x40 */ u32 reserved1[1]; u32 gen_storage6; /* 0x48 */ + u32 reserved2[3]; + u32 pers_gen_storage2; /* 0x58 */ }; #define pmu_base ((struct pmu_regs *)ZYNQMP_PMU_BASEADDR) diff --git a/drivers/bootcount/Kconfig b/drivers/bootcount/Kconfig index fa6d8e71281..0080d2a165c 100644 --- a/drivers/bootcount/Kconfig +++ b/drivers/bootcount/Kconfig @@ -164,6 +164,13 @@ config DM_BOOTCOUNT_SYSCON Accessing the backend is done using the regmap interface. +config DM_BOOTCOUNT_ZYNQMP + bool "Support ZynqMP PMUFW as a backing store for bootcount" + depends on ARCH_ZYNQMP + help + Enable support for the bootcount API by utilising the Persistent + Global General Storage Register 2 of the PMU. + endmenu endif diff --git a/drivers/bootcount/Makefile b/drivers/bootcount/Makefile index 245f8796337..0cf79e428d6 100644 --- a/drivers/bootcount/Makefile +++ b/drivers/bootcount/Makefile @@ -16,3 +16,4 @@ obj-$(CONFIG_DM_BOOTCOUNT_I2C_EEPROM) += i2c-eeprom.o obj-$(CONFIG_DM_BOOTCOUNT_I2C) += bootcount_dm_i2c.o obj-$(CONFIG_DM_BOOTCOUNT_SPI_FLASH) += spi-flash.o obj-$(CONFIG_DM_BOOTCOUNT_SYSCON) += bootcount_syscon.o +obj-$(CONFIG_DM_BOOTCOUNT_ZYNQMP) += bootcount_zynqmp.o diff --git a/drivers/bootcount/bootcount_zynqmp.c b/drivers/bootcount/bootcount_zynqmp.c new file mode 100644 index 00000000000..bc0984e2d26 --- /dev/null +++ b/drivers/bootcount/bootcount_zynqmp.c @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0+ +// SPDX-FileCopyrightText: 2024 CERN (home.cern) + +#include +#include +#include +#include +#include +#include + +static int bootcount_zynqmp_set(struct udevice *dev, const u32 val) +{ + int ret; + + ret = zynqmp_mmio_write((ulong)&pmu_base->pers_gen_storage2, 0xFF, val); + if (ret) + pr_info("%s write fail\n", __func__); + + return ret; +} + +static int bootcount_zynqmp_get(struct udevice *dev, u32 *val) +{ + int ret; + + *val = 0; + ret = zynqmp_mmio_read((ulong)&pmu_base->pers_gen_storage2, val); + if (ret) + pr_info("%s read fail\n", __func__); + + return ret; +} + +U_BOOT_DRVINFO(bootcount_zynqmp) = { + .name = "bootcount_zynqmp", +}; + +static const struct bootcount_ops bootcount_zynqmp_ops = { + .get = bootcount_zynqmp_get, + .set = bootcount_zynqmp_set, +}; + +U_BOOT_DRIVER(bootcount_zynqmp) = { + .name = "bootcount_zynqmp", + .id = UCLASS_BOOTCOUNT, + .ops = &bootcount_zynqmp_ops, +}; From 5a24caca0647c2bcc9c1fcb35ac610a35b6e11d0 Mon Sep 17 00:00:00 2001 From: Venkatesh Yadav Abbarapu Date: Thu, 14 Nov 2024 11:50:45 +0530 Subject: [PATCH 11/16] spi: cadence_qspi: Fix OSPI boot issue Moving the hw_reset function from the controller driver to the NOR framework has caused the OSPI reset not to be triggered in the Cadence driver's probe function. As a result, reading the flash ID during SPI calibration is incorrect, and the CQSPI_REG_RD_DATA_CAPTURE is set with an invalid value.This makes it unable to read the flash ID properly. To solve this problem, it's suggested to skip SPI calibration and instead retrieve the read_delay directly from the device tree. Skipping SPI calibration doesn't bring harm since there's no need for the flash golden values stored during SPI calibration. Instead, they are now read during the spi_nor_read_id call in the NOR framework. Signed-off-by: Tejas Bhumkar Signed-off-by: Venkatesh Yadav Abbarapu Link: https://lore.kernel.org/r/20241114062045.17581-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek --- drivers/spi/cadence_qspi.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 9c466f8695e..331a46d88f7 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -251,13 +251,6 @@ static int cadence_spi_probe(struct udevice *bus) priv->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, priv->ref_clk_hz); - /* Versal and Versal-NET use spi calibration to set read delay */ - if (CONFIG_IS_ENABLED(ARCH_VERSAL) || - CONFIG_IS_ENABLED(ARCH_VERSAL_NET) || - CONFIG_IS_ENABLED(ARCH_VERSAL2)) - if (priv->read_delay >= 0) - priv->read_delay = -1; - /* Reset ospi flash device */ return cadence_qspi_versal_flash_reset(bus); } From 46911346ee49edcf0d343ff52a995d465fea7af8 Mon Sep 17 00:00:00 2001 From: Venkatesh Yadav Abbarapu Date: Thu, 14 Nov 2024 10:40:47 +0530 Subject: [PATCH 12/16] arm64: versal: Enable defconfig for Micron octal flashes The Micron MT35 series octal flashes can be activated through the configuration option CONFIG_SPI_FLASH_MT35XU. To ensure their detection, enable this option in the default defconfig for octal flashes. Signed-off-by: Tejas Bhumkar Signed-off-by: Venkatesh Yadav Abbarapu Link: https://lore.kernel.org/r/20241114051047.13700-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek --- configs/xilinx_versal_virt_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index 3a4cd8f99f5..508900661be 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -110,6 +110,7 @@ CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MT35XU=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set From 93501f641b233f37ec9a96689e7eabf4142ebd82 Mon Sep 17 00:00:00 2001 From: Venkatesh Yadav Abbarapu Date: Thu, 14 Nov 2024 09:56:41 +0530 Subject: [PATCH 13/16] arm64: versal: Enable soft reset support for xspi flashes Activate the xSPI Software Reset support, which will be utilized to transition from octal DTR mode to legacy mode during shutdown and boot (if enabled). Signed-off-by: T Karthik Reddy Signed-off-by: Venkatesh Yadav Abbarapu Link: https://lore.kernel.org/r/20241114042641.22642-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek --- configs/xilinx_versal_virt_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index 508900661be..becf30433d3 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -105,6 +105,8 @@ CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_ZYNQ_SDHCI_MIN_FREQ=100000 CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SOFT_RESET=y +CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y From 253b26a72f93d66a816b5eb109aa3fdb46fb05c7 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 12 Nov 2024 14:58:48 +0100 Subject: [PATCH 14/16] arm64: zynqmp: Set default RTC device at start For RTC to start to operate there is a need to call the driver. The simple way to do it is to set default RTC instance which will call the probe and do basic initialization. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/01155f1555dbd42adc618906629f5fb45754d5a4.1731419926.git.michal.simek@amd.com --- board/xilinx/zynqmp/zynqmp_kria.env | 1 + 1 file changed, 1 insertion(+) diff --git a/board/xilinx/zynqmp/zynqmp_kria.env b/board/xilinx/zynqmp/zynqmp_kria.env index 927f398c3c3..ff3a0924de7 100644 --- a/board/xilinx/zynqmp/zynqmp_kria.env +++ b/board/xilinx/zynqmp/zynqmp_kria.env @@ -77,6 +77,7 @@ tpm_kv260=if test ${card1_rev} = A -o ${card1_rev} = B -o ${card1_rev} = Y -o ${ tpm_kd240=if test ${card1_rev} = A; then run tpm_reset; fi board_setup=\ +rtc dev 0; \ zynqmp mmio_write 0xFFCA0010 0xfff 0; \ if test ${card1_name} = SCK-KV-G; then run kv260_setup; run tpm_kv260; fi;\ if test ${card1_name} = SCK-KR-G; then run kr260_setup; run tpm_reset; fi;\ From 57066053b6f6b60a72fa82138ae92a44511cc9d4 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 15 Nov 2024 09:38:55 +0100 Subject: [PATCH 15/16] microblaze: Disable JFFS2 support JFFS2 is not maintained for quite a long time and none should be using it. Please use other filesystems for flashes like UBIFS instead. Also remove jffs to MTD map but MTD map is for example that's why it won't affect anything. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/a8239acee8886229fdbff66142c46d522e3fe851.1731659933.git.michal.simek@amd.com --- configs/microblaze-generic_defconfig | 1 - include/configs/microblaze-generic.h | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index ca78b32846a..7b3adecabb6 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -47,7 +47,6 @@ CONFIG_CMD_SAVES=y CONFIG_BOOTP_BOOTFILESIZE=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_CACHE=y -CONFIG_CMD_JFFS2=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 6740ab2be3e..3bcc4c48dc8 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -82,7 +82,7 @@ "nor0=flash-0\0"\ "mtdparts=mtdparts=flash-0:"\ "256k(u-boot),256k(env),3m(kernel),"\ - "1m(romfs),1m(cramfs),-(jffs2)\0"\ + "1m(romfs),1m(cramfs),-(fs)\0"\ "nc=setenv stdout nc;"\ "setenv stdin nc\0" \ "serial=setenv stdout serial;"\ From 383fc2f50166fded0571d41baa7826eaaa5dba97 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 15 Nov 2024 15:31:02 +0100 Subject: [PATCH 16/16] xilinx: Introduce XILINX_MINI configuration There is no common symbol which mini configurations are using and recent get_mem_top() changes adding 1.3kB without having a way to remove it. That's why introduce new symbol which can be used for removing features which are not requested by these configurations. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/aa27b72e17057fa8cbdd92a2bbb863a31c8c1226.1731681053.git.michal.simek@amd.com --- board/xilinx/Kconfig | 9 +++++++++ board/xilinx/common/board.c | 4 ++++ configs/amd_versal2_mini_defconfig | 1 + configs/amd_versal2_mini_emmc_defconfig | 1 + configs/amd_versal2_mini_ospi_defconfig | 1 + configs/amd_versal2_mini_qspi_defconfig | 1 + configs/xilinx_versal_mini_defconfig | 1 + configs/xilinx_versal_mini_emmc0_defconfig | 1 + configs/xilinx_versal_mini_emmc1_defconfig | 1 + configs/xilinx_versal_mini_ospi_defconfig | 1 + configs/xilinx_versal_mini_qspi_defconfig | 1 + configs/xilinx_versal_net_mini_defconfig | 1 + configs/xilinx_versal_net_mini_emmc_defconfig | 1 + configs/xilinx_versal_net_mini_ospi_defconfig | 1 + configs/xilinx_versal_net_mini_qspi_defconfig | 1 + configs/xilinx_zynqmp_mini_defconfig | 1 + configs/xilinx_zynqmp_mini_emmc0_defconfig | 1 + configs/xilinx_zynqmp_mini_emmc1_defconfig | 1 + configs/xilinx_zynqmp_mini_nand_defconfig | 1 + configs/xilinx_zynqmp_mini_nand_single_defconfig | 1 + configs/xilinx_zynqmp_mini_qspi_defconfig | 1 + 21 files changed, 32 insertions(+) diff --git a/board/xilinx/Kconfig b/board/xilinx/Kconfig index 0ff8440e6e0..f7152d6ee6d 100644 --- a/board/xilinx/Kconfig +++ b/board/xilinx/Kconfig @@ -40,6 +40,15 @@ config XILINX_PS_INIT_FILE endif +config XILINX_MINI + bool "Mini configuration" + depends on ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2 + help + This option disables features which are not needed for Mini U-Boot + configurations. Mini U-Boot is running in EL3 mostly on size contrained + systems. It's purpose is to program non volatile memories or running + initial memory tests. + config XILINX_OF_BOARD_DTB_ADDR hex "Default DTB pickup address" default 0x1000 if ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2 diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c index e14ed2cff00..a12dccd4c51 100644 --- a/board/xilinx/common/board.c +++ b/board/xilinx/common/board.c @@ -678,6 +678,8 @@ int ft_board_setup(void *blob, struct bd_info *bd) } #endif +#ifndef CONFIG_XILINX_MINI + #ifndef MMU_SECTION_SIZE #define MMU_SECTION_SIZE (1 * 1024 * 1024) #endif @@ -701,3 +703,5 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) return reg + size; } + +#endif diff --git a/configs/amd_versal2_mini_defconfig b/configs/amd_versal2_mini_defconfig index ea22541bfba..4c902e4dde4 100644 --- a/configs/amd_versal2_mini_defconfig +++ b/configs/amd_versal2_mini_defconfig @@ -15,6 +15,7 @@ CONFIG_DEFAULT_DEVICE_TREE="amd-versal2-mini" CONFIG_SYS_LOAD_ADDR=0xBBF80000 CONFIG_DEBUG_UART_BASE=0xf1920000 CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_XILINX_MINI=y CONFIG_SYS_MEM_RSVD_FOR_MMU=y # CONFIG_PSCI_RESET is not set CONFIG_DEBUG_UART=y diff --git a/configs/amd_versal2_mini_emmc_defconfig b/configs/amd_versal2_mini_emmc_defconfig index 6d4b261606f..da3eebe3fdf 100644 --- a/configs/amd_versal2_mini_emmc_defconfig +++ b/configs/amd_versal2_mini_emmc_defconfig @@ -12,6 +12,7 @@ CONFIG_DEFAULT_DEVICE_TREE="amd-versal2-mini" CONFIG_SYS_LOAD_ADDR=0x8000000 CONFIG_DEBUG_UART_BASE=0xf1920000 CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_XILINX_MINI=y # CONFIG_PSCI_RESET is not set CONFIG_DEBUG_UART=y # CONFIG_EXPERT is not set diff --git a/configs/amd_versal2_mini_ospi_defconfig b/configs/amd_versal2_mini_ospi_defconfig index 71bd6677838..d881cd42bff 100644 --- a/configs/amd_versal2_mini_ospi_defconfig +++ b/configs/amd_versal2_mini_ospi_defconfig @@ -15,6 +15,7 @@ CONFIG_DEFAULT_DEVICE_TREE="amd-versal2-mini" CONFIG_SYS_LOAD_ADDR=0xBBF80000 CONFIG_DEBUG_UART_BASE=0xf1920000 CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_XILINX_MINI=y CONFIG_SYS_MEM_RSVD_FOR_MMU=y # CONFIG_PSCI_RESET is not set CONFIG_DEBUG_UART=y diff --git a/configs/amd_versal2_mini_qspi_defconfig b/configs/amd_versal2_mini_qspi_defconfig index ee87d452e42..39331ef0ac3 100644 --- a/configs/amd_versal2_mini_qspi_defconfig +++ b/configs/amd_versal2_mini_qspi_defconfig @@ -15,6 +15,7 @@ CONFIG_DEFAULT_DEVICE_TREE="amd-versal2-mini" CONFIG_SYS_LOAD_ADDR=0xBBF80000 CONFIG_DEBUG_UART_BASE=0xf1920000 CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_XILINX_MINI=y CONFIG_SYS_MEM_RSVD_FOR_MMU=y # CONFIG_PSCI_RESET is not set CONFIG_DEBUG_UART=y diff --git a/configs/xilinx_versal_mini_defconfig b/configs/xilinx_versal_mini_defconfig index 7388a787386..ac3815bffde 100644 --- a/configs/xilinx_versal_mini_defconfig +++ b/configs/xilinx_versal_mini_defconfig @@ -12,6 +12,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffe0000 CONFIG_ENV_SIZE=0x80 CONFIG_DEFAULT_DEVICE_TREE="versal-mini" CONFIG_SYS_LOAD_ADDR=0x8000000 +CONFIG_XILINX_MINI=y CONFIG_SYS_MEM_RSVD_FOR_MMU=y # CONFIG_PSCI_RESET is not set CONFIG_SYS_MEMTEST_START=0x00000000 diff --git a/configs/xilinx_versal_mini_emmc0_defconfig b/configs/xilinx_versal_mini_emmc0_defconfig index a36e40dfbb3..21f241e07b1 100644 --- a/configs/xilinx_versal_mini_emmc0_defconfig +++ b/configs/xilinx_versal_mini_emmc0_defconfig @@ -12,6 +12,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10000 CONFIG_ENV_SIZE=0x80 CONFIG_DEFAULT_DEVICE_TREE="versal-mini-emmc0" CONFIG_SYS_LOAD_ADDR=0x8000000 +CONFIG_XILINX_MINI=y # CONFIG_PSCI_RESET is not set # CONFIG_EXPERT is not set CONFIG_REMAKE_ELF=y diff --git a/configs/xilinx_versal_mini_emmc1_defconfig b/configs/xilinx_versal_mini_emmc1_defconfig index 3ae2115212a..6cb654c7a4b 100644 --- a/configs/xilinx_versal_mini_emmc1_defconfig +++ b/configs/xilinx_versal_mini_emmc1_defconfig @@ -12,6 +12,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10000 CONFIG_ENV_SIZE=0x80 CONFIG_DEFAULT_DEVICE_TREE="versal-mini-emmc1" CONFIG_SYS_LOAD_ADDR=0x8000000 +CONFIG_XILINX_MINI=y # CONFIG_PSCI_RESET is not set # CONFIG_EXPERT is not set CONFIG_REMAKE_ELF=y diff --git a/configs/xilinx_versal_mini_ospi_defconfig b/configs/xilinx_versal_mini_ospi_defconfig index d0ea2b6aebd..c2a5624911a 100644 --- a/configs/xilinx_versal_mini_ospi_defconfig +++ b/configs/xilinx_versal_mini_ospi_defconfig @@ -13,6 +13,7 @@ CONFIG_ENV_SIZE=0x80 # CONFIG_DM_GPIO is not set CONFIG_DEFAULT_DEVICE_TREE="versal-mini-ospi-single" CONFIG_SYS_LOAD_ADDR=0x8000000 +CONFIG_XILINX_MINI=y CONFIG_SYS_MEM_RSVD_FOR_MMU=y CONFIG_VERSAL_NO_DDR=y # CONFIG_PSCI_RESET is not set diff --git a/configs/xilinx_versal_mini_qspi_defconfig b/configs/xilinx_versal_mini_qspi_defconfig index ef6eec075d0..4d23b353409 100644 --- a/configs/xilinx_versal_mini_qspi_defconfig +++ b/configs/xilinx_versal_mini_qspi_defconfig @@ -11,6 +11,7 @@ CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_ENV_SIZE=0x80 CONFIG_DEFAULT_DEVICE_TREE="versal-mini-qspi-single" CONFIG_SYS_LOAD_ADDR=0x8000000 +CONFIG_XILINX_MINI=y CONFIG_SYS_MEM_RSVD_FOR_MMU=y CONFIG_VERSAL_NO_DDR=y # CONFIG_PSCI_RESET is not set diff --git a/configs/xilinx_versal_net_mini_defconfig b/configs/xilinx_versal_net_mini_defconfig index 1640dfaff9e..e489f7018c9 100644 --- a/configs/xilinx_versal_net_mini_defconfig +++ b/configs/xilinx_versal_net_mini_defconfig @@ -14,6 +14,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xBBF10000 CONFIG_ENV_SIZE=0x80 CONFIG_DEFAULT_DEVICE_TREE="versal-net-mini" CONFIG_SYS_LOAD_ADDR=0xBBF00000 +CONFIG_XILINX_MINI=y CONFIG_SYS_MEM_RSVD_FOR_MMU=y # CONFIG_PSCI_RESET is not set CONFIG_SYS_MEMTEST_START=0x00000000 diff --git a/configs/xilinx_versal_net_mini_emmc_defconfig b/configs/xilinx_versal_net_mini_emmc_defconfig index 4c6159a4df1..ab201566407 100644 --- a/configs/xilinx_versal_net_mini_emmc_defconfig +++ b/configs/xilinx_versal_net_mini_emmc_defconfig @@ -10,6 +10,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10000 CONFIG_ENV_SIZE=0x80 CONFIG_DEFAULT_DEVICE_TREE="versal-net-mini-emmc" CONFIG_SYS_LOAD_ADDR=0x8000000 +CONFIG_XILINX_MINI=y # CONFIG_PSCI_RESET is not set # CONFIG_EXPERT is not set CONFIG_REMAKE_ELF=y diff --git a/configs/xilinx_versal_net_mini_ospi_defconfig b/configs/xilinx_versal_net_mini_ospi_defconfig index 071eeb8197b..f5864b5b826 100644 --- a/configs/xilinx_versal_net_mini_ospi_defconfig +++ b/configs/xilinx_versal_net_mini_ospi_defconfig @@ -13,6 +13,7 @@ CONFIG_ENV_SIZE=0x80 # CONFIG_DM_GPIO is not set CONFIG_DEFAULT_DEVICE_TREE="versal-net-mini-ospi-single" CONFIG_SYS_LOAD_ADDR=0xBBF80000 +CONFIG_XILINX_MINI=y CONFIG_SYS_MEM_RSVD_FOR_MMU=y # CONFIG_PSCI_RESET is not set CONFIG_LTO=y diff --git a/configs/xilinx_versal_net_mini_qspi_defconfig b/configs/xilinx_versal_net_mini_qspi_defconfig index 227c45df28c..8453be5a590 100644 --- a/configs/xilinx_versal_net_mini_qspi_defconfig +++ b/configs/xilinx_versal_net_mini_qspi_defconfig @@ -11,6 +11,7 @@ CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_ENV_SIZE=0x80 CONFIG_DEFAULT_DEVICE_TREE="versal-net-mini-qspi-single" CONFIG_SYS_LOAD_ADDR=0xBBF80000 +CONFIG_XILINX_MINI=y CONFIG_SYS_MEM_RSVD_FOR_MMU=y # CONFIG_PSCI_RESET is not set CONFIG_LTO=y diff --git a/configs/xilinx_zynqmp_mini_defconfig b/configs/xilinx_zynqmp_mini_defconfig index 7aab69c9e46..b58cf8af74b 100644 --- a/configs/xilinx_zynqmp_mini_defconfig +++ b/configs/xilinx_zynqmp_mini_defconfig @@ -9,6 +9,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffe0000 CONFIG_ENV_SIZE=0x80 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini" CONFIG_SYS_LOAD_ADDR=0x8000000 +CONFIG_XILINX_MINI=y CONFIG_SYS_MEM_RSVD_FOR_MMU=y CONFIG_SYS_MEMTEST_START=0x00000000 CONFIG_SYS_MEMTEST_END=0x00001000 diff --git a/configs/xilinx_zynqmp_mini_emmc0_defconfig b/configs/xilinx_zynqmp_mini_emmc0_defconfig index c56b1e830d6..f47880b6db4 100644 --- a/configs/xilinx_zynqmp_mini_emmc0_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc0_defconfig @@ -15,6 +15,7 @@ CONFIG_SPL_SYS_MALLOC_F_LEN=0x600 CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SYS_LOAD_ADDR=0x8000000 CONFIG_SPL=y +CONFIG_XILINX_MINI=y CONFIG_REMAKE_ELF=y # CONFIG_MP is not set # CONFIG_EFI_LOADER is not set diff --git a/configs/xilinx_zynqmp_mini_emmc1_defconfig b/configs/xilinx_zynqmp_mini_emmc1_defconfig index a8dbf0056da..fc0070adbe1 100644 --- a/configs/xilinx_zynqmp_mini_emmc1_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc1_defconfig @@ -15,6 +15,7 @@ CONFIG_SPL_SYS_MALLOC_F_LEN=0x600 CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SYS_LOAD_ADDR=0x8000000 CONFIG_SPL=y +CONFIG_XILINX_MINI=y CONFIG_REMAKE_ELF=y # CONFIG_MP is not set # CONFIG_EFI_LOADER is not set diff --git a/configs/xilinx_zynqmp_mini_nand_defconfig b/configs/xilinx_zynqmp_mini_nand_defconfig index ba8f02c5b11..6a7541fe9d5 100644 --- a/configs/xilinx_zynqmp_mini_nand_defconfig +++ b/configs/xilinx_zynqmp_mini_nand_defconfig @@ -10,6 +10,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40000 CONFIG_ENV_SIZE=0x80 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-nand" CONFIG_SYS_LOAD_ADDR=0x8000000 +CONFIG_XILINX_MINI=y CONFIG_REMAKE_ELF=y # CONFIG_MP is not set # CONFIG_EFI_LOADER is not set diff --git a/configs/xilinx_zynqmp_mini_nand_single_defconfig b/configs/xilinx_zynqmp_mini_nand_single_defconfig index a8a0055f2e5..3643caea3ce 100644 --- a/configs/xilinx_zynqmp_mini_nand_single_defconfig +++ b/configs/xilinx_zynqmp_mini_nand_single_defconfig @@ -10,6 +10,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40000 CONFIG_ENV_SIZE=0x80 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-nand" CONFIG_SYS_LOAD_ADDR=0x8000000 +CONFIG_XILINX_MINI=y CONFIG_REMAKE_ELF=y # CONFIG_MP is not set # CONFIG_EFI_LOADER is not set diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig index c08b10c6944..a60403d82c2 100644 --- a/configs/xilinx_zynqmp_mini_qspi_defconfig +++ b/configs/xilinx_zynqmp_mini_qspi_defconfig @@ -15,6 +15,7 @@ CONFIG_SYS_LOAD_ADDR=0x8000000 CONFIG_SPL=y # CONFIG_SPL_FS_FAT is not set # CONFIG_SPL_LIBDISK_SUPPORT is not set +CONFIG_XILINX_MINI=y CONFIG_SYS_MEM_RSVD_FOR_MMU=y CONFIG_ZYNQMP_NO_DDR=y # CONFIG_PSCI_RESET is not set