From 308bd746639a7d144a9cf563ac7449312841386d Mon Sep 17 00:00:00 2001 From: Michael Trimarchi Date: Thu, 22 Sep 2022 15:39:37 +0200 Subject: [PATCH 01/12] cmd: nand: Extend nand info to print ecc information Extract the information about ecc strength and ecc step size from mtd controller. This information is usefull to check if what we think as ecc is what we really configured. Signed-off-by: Michael Trimarchi Reviewed-by: Dario Binacchi Link: https://lore.kernel.org/all/20220922133937.277463-1-michael@amarulasolutions.com Signed-off-by: Dario Binacchi --- cmd/nand.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/cmd/nand.c b/cmd/nand.c index 5bb43794e90..9a723f57579 100644 --- a/cmd/nand.c +++ b/cmd/nand.c @@ -417,12 +417,14 @@ static void nand_print_and_set_info(int idx) printf("%dx ", chip->numchips); printf("%s, sector size %u KiB\n", mtd->name, mtd->erasesize >> 10); - printf(" Page size %8d b\n", mtd->writesize); - printf(" OOB size %8d b\n", mtd->oobsize); - printf(" Erase size %8d b\n", mtd->erasesize); - printf(" subpagesize %8d b\n", chip->subpagesize); - printf(" options 0x%08x\n", chip->options); - printf(" bbt options 0x%08x\n", chip->bbt_options); + printf(" Page size %8d b\n", mtd->writesize); + printf(" OOB size %8d b\n", mtd->oobsize); + printf(" Erase size %8d b\n", mtd->erasesize); + printf(" ecc strength %8d bits\n", mtd->ecc_strength); + printf(" ecc step size %8d b\n", mtd->ecc_step_size); + printf(" subpagesize %8d b\n", chip->subpagesize); + printf(" options 0x%08x\n", chip->options); + printf(" bbt options 0x%08x\n", chip->bbt_options); /* Set geometry info */ env_set_hex("nand_writesize", mtd->writesize); From c6bafdae50f2f55fd09dd46375c918a5b96328c5 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 11 Oct 2022 14:49:59 +0300 Subject: [PATCH 02/12] mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h We want to get rid of so don't enforce it for new platforms. This also means GPMC_MAX CS doesn't have to be defined by platform code. Define it locally here for now. Signed-off-by: Roger Quadros Reviewed-by: Michael Trimarchi Link: https://lore.kernel.org/all/20221011115012.6181-2-rogerq@kernel.org Signed-off-by: Dario Binacchi --- drivers/mtd/nand/raw/omap_gpmc.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index 8b9ff4de189..7e9ccf78789 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -8,7 +8,11 @@ #include #include #include + +#ifdef CONFIG_ARCH_OMAP2PLUS #include +#endif + #include #include #include @@ -17,6 +21,10 @@ #include #include +#ifndef GPMC_MAX_CS +#define GPMC_MAX_CS 4 +#endif + #define BADBLOCK_MARKER_LENGTH 2 #define SECTOR_BYTES 512 #define ECCCLEAR (0x1 << 8) From 472229fcfc84e850b78c39f86638c194f78ab89d Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 11 Oct 2022 14:50:00 +0300 Subject: [PATCH 03/12] mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms The GPMC module is present on some K2 and K3 SoCs. Enable building GPMC NAND driver for K2/K3 platforms. Signed-off-by: Roger Quadros Reviewed-By: Michael Trimarchi Link: https://lore.kernel.org/all/20221011115012.6181-3-rogerq@kernel.org Signed-off-by: Dario Binacchi --- drivers/mtd/nand/raw/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index da2c5795bc3..8aaba8b1a2c 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -197,7 +197,7 @@ config NAND_LPC32XX_SLC config NAND_OMAP_GPMC bool "Support OMAP GPMC NAND controller" - depends on ARCH_OMAP2PLUS + depends on ARCH_OMAP2PLUS || ARCH_KEYSTONE || ARCH_K3 help Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms. GPMC controller is used for parallel NAND flash devices, and can From 7e4a494c5f676c7a16a28ac36b9fdbd84022a400 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 11 Oct 2022 14:50:01 +0300 Subject: [PATCH 04/12] mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms Pointer size cannot be assumed to be 32-bit, so use use uintptr_t instead of uint32_t. Fixes the below build warning on 64-bit builds. drivers/mtd/nand/raw/omap_gpmc.c:439:10: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] head = ((uint32_t) buf) % 4; Signed-off-by: Roger Quadros Reviewed-by: Michael Trimarchi Link: https://lore.kernel.org/all/20221011115012.6181-4-rogerq@kernel.org Signed-off-by: Dario Binacchi --- drivers/mtd/nand/raw/omap_gpmc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index 7e9ccf78789..d62c3e6fce5 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -438,14 +438,14 @@ static inline void omap_nand_read(struct mtd_info *mtd, uint8_t *buf, int len) static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len) { int ret; - uint32_t head, tail; + uintptr_t head, tail; struct nand_chip *chip = mtd_to_nand(mtd); /* * If the destination buffer is unaligned, start with reading * the overlap byte-wise. */ - head = ((uint32_t) buf) % 4; + head = ((uintptr_t)buf) % 4; if (head) { omap_nand_read(mtd, buf, head); buf += head; From cd72a950e0aaba0ea7e9cb1d03ff2f1ca0ca037a Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 11 Oct 2022 14:50:02 +0300 Subject: [PATCH 05/12] mtd: rawnand: omap_gpmc: Optimize NAND reads Rename omap_nand_read() to omap_nand_read_buf() to reflect actual behaviour. Use FIFO read address instead of raw read address for reads. The GPMC automatically converts 32-bit/16-bit reads to NAND device specific reads (8/16 bit). Use the largest possible read granularity size for more efficient reads. Signed-off-by: Roger Quadros Reviewed-by: Michael Trimarchi Link: https://lore.kernel.org/all/20221011115012.6181-5-rogerq@kernel.org Signed-off-by: Dario Binacchi --- drivers/mtd/nand/raw/omap_gpmc.c | 49 ++++++++++++++++++-------------- 1 file changed, 28 insertions(+), 21 deletions(-) diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index d62c3e6fce5..b36fe762b39 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -55,6 +55,7 @@ struct omap_nand_info { enum omap_ecc ecc_scheme; uint8_t cs; uint8_t ws; /* wait status pin (0,1) */ + void __iomem *fifo; }; /* We are wasting a bit of memory but al least we are safe */ @@ -350,6 +351,20 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, return 0; } +static inline void omap_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct omap_nand_info *info = nand_get_controller_data(chip); + u32 alignment = ((uintptr_t)buf | len) & 3; + + if (alignment & 1) + readsb(info->fifo, buf, len); + else if (alignment & 3) + readsw(info->fifo, buf, len >> 1); + else + readsl(info->fifo, buf, len >> 2); +} + #ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH #define PREFETCH_CONFIG1_CS_SHIFT 24 @@ -415,7 +430,7 @@ static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int le cnt = PREFETCH_STATUS_FIFO_CNT(cnt); for (i = 0; i < cnt / 4; i++) { - *buf++ = readl(CONFIG_SYS_NAND_BASE); + *buf++ = readl(info->fifo); len -= 4; } } while (len); @@ -425,16 +440,6 @@ static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int le return 0; } -static inline void omap_nand_read(struct mtd_info *mtd, uint8_t *buf, int len) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - - if (chip->options & NAND_BUSWIDTH_16) - nand_read_buf16(mtd, buf, len); - else - nand_read_buf(mtd, buf, len); -} - static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len) { int ret; @@ -447,7 +452,7 @@ static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len) */ head = ((uintptr_t)buf) % 4; if (head) { - omap_nand_read(mtd, buf, head); + omap_nand_read_buf(mtd, buf, head); buf += head; len -= head; } @@ -461,10 +466,10 @@ static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len) ret = __read_prefetch_aligned(chip, (uint32_t *)buf, len - tail); if (ret < 0) { /* fallback in case the prefetch engine is busy */ - omap_nand_read(mtd, buf, len); + omap_nand_read_buf(mtd, buf, len); } else if (tail) { buf += len - tail; - omap_nand_read(mtd, buf, tail); + omap_nand_read_buf(mtd, buf, tail); } } #endif /* CONFIG_NAND_OMAP_GPMC_PREFETCH */ @@ -1001,6 +1006,8 @@ int board_nand_init(struct nand_chip *nand) int32_t gpmc_config = 0; int cs = cs_next++; int err = 0; + struct omap_nand_info *info; + /* * xloader/Uboot's gpmc configuration would have configured GPMC for * nand type of memory. The following logic scans and latches on to the @@ -1029,9 +1036,12 @@ int board_nand_init(struct nand_chip *nand) nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat; nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd; - omap_nand_info[cs].control = NULL; - omap_nand_info[cs].cs = cs; - omap_nand_info[cs].ws = wscfg[cs]; + + info = &omap_nand_info[cs]; + info->control = NULL; + info->cs = cs; + info->ws = wscfg[cs]; + info->fifo = (void __iomem *)CONFIG_SYS_NAND_BASE; nand_set_controller_data(nand, &omap_nand_info[cs]); nand->cmd_ctrl = omap_nand_hwcontrol; nand->options |= NAND_NO_PADDING | NAND_CACHEPRG; @@ -1062,10 +1072,7 @@ int board_nand_init(struct nand_chip *nand) #ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH nand->read_buf = omap_nand_read_prefetch; #else - if (nand->options & NAND_BUSWIDTH_16) - nand->read_buf = nand_read_buf16; - else - nand->read_buf = nand_read_buf; + nand->read_buf = omap_nand_read_buf; #endif nand->dev_ready = omap_dev_ready; From 664d5369269f80d0883ede4573425e3546c87080 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 11 Oct 2022 14:50:05 +0300 Subject: [PATCH 06/12] mtd: rawnand: nand_spl_loaders: Fix cast type build warning Fixes the below build warning on 64-bit platforms. drivers/mtd/nand/raw/nand_spl_loaders.c:26:21: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] dst = (void *)((int)dst - page_offset); Signed-off-by: Roger Quadros Reviewed-by: Michael Trimarchi Link: https://lore.kernel.org/all/20221011115012.6181-8-rogerq@kernel.org Signed-off-by: Dario Binacchi --- drivers/mtd/nand/raw/nand_spl_loaders.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/nand_spl_loaders.c b/drivers/mtd/nand/raw/nand_spl_loaders.c index 4befc75c047..156b44d8358 100644 --- a/drivers/mtd/nand/raw/nand_spl_loaders.c +++ b/drivers/mtd/nand/raw/nand_spl_loaders.c @@ -23,7 +23,7 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst) if (unlikely(page_offset)) { memmove(dst, dst + page_offset, CONFIG_SYS_NAND_PAGE_SIZE); - dst = (void *)((int)dst - page_offset); + dst = (void *)(dst - page_offset); page_offset = 0; } dst += CONFIG_SYS_NAND_PAGE_SIZE; From ec2c9240d508e67eca3d633ecb7f4740e2673a6a Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 11 Oct 2022 14:50:06 +0300 Subject: [PATCH 07/12] mtd: rawnand: omap_gpmc: Reduce .bss usage Allocate omap_ecclayout on the heap as we have limited .bss space on AM64 R5 SPL configuration. Reduces .bss usage by 2984 bytes. Signed-off-by: Roger Quadros Reviewed-By: Michael Trimarchi Link: https://lore.kernel.org/all/20221011115012.6181-9-rogerq@kernel.org Signed-off-by: Dario Binacchi --- drivers/mtd/nand/raw/omap_gpmc.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index b36fe762b39..69fc09be097 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -37,7 +37,6 @@ static u8 bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2, 0x97, 0x79, 0xe5, 0x24, 0xb5}; #endif static uint8_t cs_next; -static __maybe_unused struct nand_ecclayout omap_ecclayout; #if defined(CONFIG_NAND_OMAP_GPMC_WSCFG) static const int8_t wscfg[CONFIG_SYS_MAX_NAND_DEVICE] = @@ -753,7 +752,7 @@ static void __maybe_unused omap_free_bch(struct mtd_info *mtd) static int omap_select_ecc_scheme(struct nand_chip *nand, enum omap_ecc ecc_scheme, unsigned int pagesize, unsigned int oobsize) { struct omap_nand_info *info = nand_get_controller_data(nand); - struct nand_ecclayout *ecclayout = &omap_ecclayout; + struct nand_ecclayout *ecclayout = nand->ecc.layout; int eccsteps = pagesize / SECTOR_BYTES; int i; @@ -1046,7 +1045,9 @@ int board_nand_init(struct nand_chip *nand) nand->cmd_ctrl = omap_nand_hwcontrol; nand->options |= NAND_NO_PADDING | NAND_CACHEPRG; nand->chip_delay = 100; - nand->ecc.layout = &omap_ecclayout; + nand->ecc.layout = kzalloc(sizeof(*nand->ecc.layout), GFP_KERNEL); + if (!nand->ecc.layout) + return -ENOMEM; /* configure driver and controller based on NAND device bus-width */ gpmc_config = readl(&gpmc_cfg->cs[cs].config1); From c21b0ca525bd818428a62dd267697071822cc9a9 Mon Sep 17 00:00:00 2001 From: Michael Trimarchi Date: Fri, 21 Oct 2022 08:05:36 +0200 Subject: [PATCH 08/12] mtd: nand: make Samsung SLC NAND usable again MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Upstream linux commit 69fc01296c9281 commit a1286a1fc416 ("mtd: nand: Move Samsung specific init/detection logic in nand_samsung.c") introduced a regression for Samsung SLC NAND chips. Prior to this commit chip->bits_per_cell was initialized by calling nand_get_bits_per_cell() before using nand_is_slc(). With the offending commit this call is skipped, leaving chip->bits_per_cell cleared to zero when the manufacturer specific '.detect' function calls nand_is_slc() which in turn interprets bits_per_cell != 1 as indication for an MLC chip. The effect is that e.g. a K9F1G08U0F NAND chip is falsely detected as MLC NAND with 4KiB page size rather than SLC with 2KiB page size. Add a call to nand_get_bits_per_cell() before calling the .detect hook function in nand_manufacturer_detect(), so that the nand_is_slc() calls in the manufacturer specific code will return correct results. Reported-by: Marcin Gołaś Signed-off-by: Michael Trimarchi Reviewed-by: Dario Binacchi Link: https://lore.kernel.org/all/20221021060536.11747-1-michael@amarulasolutions.com Signed-off-by: Dario Binacchi --- drivers/mtd/nand/raw/nand_base.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 215b9ba84fd..bc61ad03eb0 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -4171,10 +4171,13 @@ static void nand_manufacturer_detect(struct nand_chip *chip) * nand_decode_ext_id() otherwise. */ if (chip->manufacturer.desc && chip->manufacturer.desc->ops && - chip->manufacturer.desc->ops->detect) + chip->manufacturer.desc->ops->detect) { + /* The 3rd id byte holds MLC / multichip data */ + chip->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]); chip->manufacturer.desc->ops->detect(chip); - else + } else { nand_decode_ext_id(chip); + } } /* From d09807ad144cb2fe3745a58caadf9a4192038839 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Sun, 30 Oct 2022 15:14:13 +0100 Subject: [PATCH 09/12] cmd: mtd: check if a block has to be skipped or erased As reported by patch [1], the `mtd erase' command should not erase bad blocks. To force bad block erasing you have to use the `mtd erase.dontskipbad' command. This patch tries to fix the same issue without modifying code taken from the linux kernel, in order to make further upgrades easier. [1] https://lore.kernel.org/all/20221006031501.110290-2-mikhail.kshevetskiy@iopsys.eu/ Suggested-by: Michael Trimarchi Co-developed-by: Michael Trimarchi Signed-off-by: Michael Trimarchi Co-developed-by: Mikhail Kshevetskiy Signed-off-by: Mikhail Kshevetskiy Tested-by: Mikhail Kshevetskiy Signed-off-by: Dario Binacchi --- cmd/mtd.c | 28 ++++++++++++++++++++-------- 1 file changed, 20 insertions(+), 8 deletions(-) diff --git a/cmd/mtd.c b/cmd/mtd.c index ad5cc9827d5..eb6e2d6892f 100644 --- a/cmd/mtd.c +++ b/cmd/mtd.c @@ -434,19 +434,31 @@ static int do_mtd_erase(struct cmd_tbl *cmdtp, int flag, int argc, erase_op.mtd = mtd; erase_op.addr = off; erase_op.len = mtd->erasesize; - erase_op.scrub = scrub; while (len) { - ret = mtd_erase(mtd, &erase_op); + if (!scrub) { + ret = mtd_block_isbad(mtd, erase_op.addr); + if (ret < 0) { + printf("Failed to get bad block at 0x%08llx\n", + erase_op.addr); + ret = CMD_RET_FAILURE; + goto out_put_mtd; + } - if (ret) { - /* Abort if its not a bad block error */ - if (ret != -EIO) - break; - printf("Skipping bad block at 0x%08llx\n", - erase_op.addr); + if (ret > 0) { + printf("Skipping bad block at 0x%08llx\n", + erase_op.addr); + ret = 0; + len -= mtd->erasesize; + erase_op.addr += mtd->erasesize; + continue; + } } + ret = mtd_erase(mtd, &erase_op); + if (ret && ret != -EIO) + break; + len -= mtd->erasesize; erase_op.addr += mtd->erasesize; } From 670789f5ba2f3330b137f637deb47671b8720c33 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Tue, 8 Nov 2022 10:07:19 +0100 Subject: [PATCH 10/12] mtd: nand: drop EXPORT_SYMBOL_GPL for nanddev_erase() This function is only used within this module, so it is no longer necessary to use EXPORT_SYMBOL_GPL(). This patch parallels the work done in the following patch: https://lore.kernel.org/linux-mtd/20221018170205.1733958-1-dario.binacchi@amarulasolutions.com Signed-off-by: Dario Binacchi Reviewed-By: Michael Trimarchi Link: https://lore.kernel.org/all/20221108090719.3631621-1-dario.binacchi@amarulasolutions.com --- drivers/mtd/nand/core.c | 3 +-- include/linux/mtd/nand.h | 1 - 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/mtd/nand/core.c b/drivers/mtd/nand/core.c index 99c29670c75..4b9dd6a9269 100644 --- a/drivers/mtd/nand/core.c +++ b/drivers/mtd/nand/core.c @@ -129,7 +129,7 @@ EXPORT_SYMBOL_GPL(nanddev_isreserved); * * Return: 0 in case of success, a negative error code otherwise. */ -int nanddev_erase(struct nand_device *nand, const struct nand_pos *pos) +static int nanddev_erase(struct nand_device *nand, const struct nand_pos *pos) { unsigned int entry; @@ -147,7 +147,6 @@ int nanddev_erase(struct nand_device *nand, const struct nand_pos *pos) return nand->ops->erase(nand, pos); } -EXPORT_SYMBOL_GPL(nanddev_erase); /** * nanddev_mtd_erase() - Generic mtd->_erase() implementation for NAND devices diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 7774c17ad5d..aeb38dec2e0 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -691,7 +691,6 @@ static inline bool nanddev_io_iter_end(struct nand_device *nand, bool nanddev_isbad(struct nand_device *nand, const struct nand_pos *pos); bool nanddev_isreserved(struct nand_device *nand, const struct nand_pos *pos); -int nanddev_erase(struct nand_device *nand, const struct nand_pos *pos); int nanddev_markbad(struct nand_device *nand, const struct nand_pos *pos); /* BBT related functions */ From 17c2ccde22c7374df452db057b185b4c9f9b6bd0 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Sun, 20 Nov 2022 10:57:04 +0100 Subject: [PATCH 11/12] mtd: nand: mxs_nand_spl: don't read useless pages The patch prevents pages beyond the last from being unnecessarily read. This occurs when the last page to be read is not the last page of the last block. Before this change we would have read all the pages up to the end of the last block. Suggested-by: Michael Trimarchi Co-developed-by: Michael Trimarchi Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi Acked-by: Michael Trimarchi Link: https://lore.kernel.org/all/20221120095705.3019295-1-dario.binacchi@amarulasolutions.com --- drivers/mtd/nand/raw/mxs_nand_spl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/mxs_nand_spl.c b/drivers/mtd/nand/raw/mxs_nand_spl.c index ef03b7789dd..300662994cf 100644 --- a/drivers/mtd/nand/raw/mxs_nand_spl.c +++ b/drivers/mtd/nand/raw/mxs_nand_spl.c @@ -257,7 +257,7 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst) while (block <= lastblock && size > 0) { if (!is_badblock(mtd, mtd->erasesize * block, 1)) { /* Skip bad blocks */ - while (page < nand_page_per_block) { + while (page < nand_page_per_block && size) { int curr_page = nand_page_per_block * block + page; if (mxs_read_page_ecc(mtd, page_buf, curr_page) < 0) { From fda2253d121f05921e419edffe615c607917792a Mon Sep 17 00:00:00 2001 From: Dai Okamura Date: Fri, 9 Dec 2022 20:40:21 +0900 Subject: [PATCH 12/12] spl: spl_legacy: fix invalid offset in SPL_COPY_PAYLOAD_ONLY This fixes the header offset calculation. This issue was found on uniphier v7 SoCs with SPL. Fixes: 06377c5a1f ("spl: spl_legacy: Fix NAND boot on OMAP3 BeagleBoard") Signed-off-by: Dai Okamura Reviewed-By: Michael Trimarchi Acked-by: Michael Trimarchi Link: https://lore.kernel.org/all/20221209114021.3074978-1-okamura.dai@socionext.com Signed-off-by: Dario Binacchi --- common/spl/spl_legacy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/common/spl/spl_legacy.c b/common/spl/spl_legacy.c index 4c7f44687e8..16851c55eb5 100644 --- a/common/spl/spl_legacy.c +++ b/common/spl/spl_legacy.c @@ -106,7 +106,7 @@ int spl_load_legacy_img(struct spl_image_info *spl_image, * is set */ if (spl_image->flags & SPL_COPY_PAYLOAD_ONLY) - dataptr += sizeof(hdr); + dataptr += sizeof(*hdr); load->read(load, dataptr, spl_image->size, (void *)(unsigned long)spl_image->load_addr); @@ -116,7 +116,7 @@ int spl_load_legacy_img(struct spl_image_info *spl_image, lzma_len = LZMA_LEN; /* dataptr points to compressed payload */ - dataptr = offset + sizeof(hdr); + dataptr = offset + sizeof(*hdr); debug("LZMA: Decompressing %08lx to %08lx\n", dataptr, spl_image->load_addr);