Merge tag 'v2026.01-rc4' into next

Prepare v2026.01-rc4

include/configs/exynos-mobile.h

@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Samsung Exynos Generic Board Configuration (for mobile devices)
+ *
+ * Copyright (C) 2025 Kaustabh Chakraborty <kauschluss@disroot.org>
+ */
+
+#ifndef __CONFIG_EXYNOS_MOBILE_H
+#define __CONFIG_EXYNOS_MOBILE_H
+
+#define CPU_RELEASE_ADDR	secondary_boot_addr
+#define CFG_SYS_BAUDRATE_TABLE	{9600, 115200}
+
+#endif /* __CONFIG_EXYNOS_MOBILE_H */

include/configs/ironhide.h

@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+#ifndef __IRONHIDE_H
+#define __IRONHIDE_H
+
+#include "rcar-gen5-common.h"
+
+#endif /* __IRONHIDE_H */

include/configs/rcar-gen5-common.h

@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2025 Renesas Electronics Corporation
+ */
+
+#ifndef __RCAR_GEN5_COMMON_H
+#define __RCAR_GEN5_COMMON_H
+
+#include <asm/arch/renesas.h>
+
+/* Console */
+#define CFG_SYS_BAUDRATE_TABLE		{ 38400, 115200, 921600, 1843200, 3250000 }
+
+/* Memory */
+#define DRAM_RSV_SIZE			0x08000000
+#define CFG_SYS_SDRAM_BASE		(0x40000000 + DRAM_RSV_SIZE)
+#define CFG_SYS_SDRAM_SIZE		(0x80000000u - DRAM_RSV_SIZE)
+#define CFG_MAX_MEM_MAPPED		(0x80000000u - DRAM_RSV_SIZE)
+
+/* Environment setting */
+#define CFG_EXTRA_ENV_SETTINGS		\
+	"bootm_size=0x10000000\0"
+
+#endif	/* __RCAR_GEN5_COMMON_H */

include/configs/s5p4418_nanopi2.h

@@ -139,7 +139,6 @@
 #endif
 
 #define CFG_EXTRA_ENV_SETTINGS				\
-	"fdt_high=0xffffffff\0"					\
 	"initrd_high=0xffffffff\0"				\
 	"rootdev=" __stringify(CONFIG_ROOT_DEV) "\0"		\
 	"rootpart=" __stringify(CONFIG_ROOT_PART) "\0"		\

include/configs/socfpga_vining_fpga.h

@@ -40,7 +40,6 @@
 	"hostname=vining_fpga\0"					\
 	"kernel_addr_r=0x10000000\0"					\
 	"fdt_addr_r=0x20000000\0"					\
-	"fdt_high=0xffffffff\0"						\
 	"initrd_high=0xffffffff\0"					\
 	"dfu_alt_info=qspi0 sf 0:0;qspi1 sf 0:1\0"			\
 	"mtdparts_0_16m=ff705000.spi.0:" /* 16MiB+128MiB SF config */	\

include/dt-bindings/clock/r8a78000-clock-scmi.h

@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ *
+ * IDs match SCP 4.27
+ */
+
+#ifndef __DT_BINDINGS_R8A78000_SCMI_CLOCK_H__
+#define __DT_BINDINGS_R8A78000_SCMI_CLOCK_H__
+
+/*
+ * These definition indices match the Clock ID defined by SCP FW 4.27.
+ */
+
+#define SCP_CLOCK_ID_MDLC_UFS0		202
+#define SCP_CLOCK_ID_MDLC_UFS1		203
+#define SCP_CLOCK_ID_MDLC_SDHI0		204
+
+#define SCP_CLOCK_ID_MDLC_XPCS0		316
+#define SCP_CLOCK_ID_MDLC_XPCS1		317
+#define SCP_CLOCK_ID_MDLC_XPCS2		318
+#define SCP_CLOCK_ID_MDLC_XPCS3		319
+#define SCP_CLOCK_ID_MDLC_XPCS4		320
+#define SCP_CLOCK_ID_MDLC_XPCS5		321
+#define SCP_CLOCK_ID_MDLC_XPCS6		322
+#define SCP_CLOCK_ID_MDLC_XPCS7		323
+#define SCP_CLOCK_ID_MDLC_RSW3		324
+#define SCP_CLOCK_ID_MDLC_RSW3TSN	325
+#define SCP_CLOCK_ID_MDLC_RSW3AES	326
+#define SCP_CLOCK_ID_MDLC_RSW3TSNTES0	327
+#define SCP_CLOCK_ID_MDLC_RSW3TSNTES1	328
+#define SCP_CLOCK_ID_MDLC_RSW3TSNTES2	329
+#define SCP_CLOCK_ID_MDLC_RSW3TSNTES3	330
+#define SCP_CLOCK_ID_MDLC_RSW3TSNTES4	331
+#define SCP_CLOCK_ID_MDLC_RSW3TSNTES5	332
+#define SCP_CLOCK_ID_MDLC_RSW3TSNTES6	333
+#define SCP_CLOCK_ID_MDLC_RSW3TSNTES7	334
+#define SCP_CLOCK_ID_MDLC_RSW3MFWD	335
+
+#define SCP_CLOCK_ID_MDLC_MPPHY01	344
+#define SCP_CLOCK_ID_MDLC_MPPHY11	345
+#define SCP_CLOCK_ID_MDLC_MPPHY21	346
+#define SCP_CLOCK_ID_MDLC_MPPHY31	347
+#define SCP_CLOCK_ID_MDLC_MPPHY02	348
+
+#endif /* __DT_BINDINGS_R8A78000_SCMI_CLOCK_H__ */

include/dt-bindings/power/r8a78000-power-scmi.h

@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ *
+ * IDs match SCP 4.27
+ */
+
+#ifndef __DT_BINDINGS_R8A78000_SCMI_POWER_H__
+#define __DT_BINDINGS_R8A78000_SCMI_POWER_H__
+
+/*
+ * These power domain indices match the Power Domain ID defined by SCP FW 4.27.
+ */
+
+#define X5H_POWER_DOMAIN_ID_UFS0	12
+#define X5H_POWER_DOMAIN_ID_UFS1	13
+
+#define X5H_POWER_DOMAIN_ID_RSW		15
+
+#define X5H_POWER_DOMAIN_ID_MPP0	17
+#define X5H_POWER_DOMAIN_ID_MPP1	18
+#define X5H_POWER_DOMAIN_ID_MPP2	19
+#define X5H_POWER_DOMAIN_ID_MPP3	20
+
+#endif /* __DT_BINDINGS_R8A78000_SCMI_POWER_H__ */

include/dt-bindings/reset/r8a78000-reset-scmi.h

@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ *
+ * IDs match SCP 4.27
+ */
+
+#ifndef __DT_BINDINGS_R8A78000_SCMI_RESET_H__
+#define __DT_BINDINGS_R8A78000_SCMI_RESET_H__
+
+/*
+ * These definition indices match the Reset ID defined by SCP FW 4.27.
+ */
+
+#define SCP_RESET_DOMAIN_ID_UFS0	202
+#define SCP_RESET_DOMAIN_ID_UFS1	203
+
+#define SCP_RESET_DOMAIN_ID_XPCS0	316
+#define SCP_RESET_DOMAIN_ID_XPCS1	317
+#define SCP_RESET_DOMAIN_ID_XPCS2	318
+#define SCP_RESET_DOMAIN_ID_XPCS3	319
+#define SCP_RESET_DOMAIN_ID_XPCS4	320
+#define SCP_RESET_DOMAIN_ID_XPCS5	321
+#define SCP_RESET_DOMAIN_ID_XPCS6	322
+#define SCP_RESET_DOMAIN_ID_XPCS7	323
+
+#define SCP_RESET_DOMAIN_ID_MPPHY01	344
+#define SCP_RESET_DOMAIN_ID_MPPHY11	345
+#define SCP_RESET_DOMAIN_ID_MPPHY21	346
+#define SCP_RESET_DOMAIN_ID_MPPHY31	347
+#define SCP_RESET_DOMAIN_ID_MPPHY02	348
+
+#endif /* __DT_BINDINGS_R8A78000_SCMI_RESET_H__ */

include/env/adi/adi_boot.env

@@ -39,7 +39,7 @@ addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmas
 /* Boot modes are selectable and should be defined in the board env before including */
 #if defined(USE_NFS)
 // rootpath is set by CONFIG_ROOTPATH
-nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}${rootpath},tcp,nfsvers=3 ${adi_bootargs}
+nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath},tcp,nfsvers=3 ${adi_bootargs}
 nfsboot=run init_ethernet;
 	tftp ${loadaddr} ${tftp_dir_prefix}${imagefile};
 	run nfsargs;