Merge tag 'u-boot-rockchip-2026.10-20260813' of https://git.u-boot-project.org/u-boot/custodians/u-boot-rockchip

CI: https://git.u-boot-project.org/u-boot/custodians/u-boot-rockchip/-/pipelines/972

- Disable JTAG for RK3576. Fix for boards potentially not being able to
  use SD card anymore due to automatic switch to JTAG based on level of
  one specific pin,

arch/arm/mach-rockchip/rk3576/rk3576.c

@@ -9,7 +9,8 @@
 #include <misc.h>
 #include <asm/armv8/mmu.h>
 #include <asm/arch-rockchip/bootrom.h>
-#include <asm/arch-rockchip/hardware.h>
+#include <asm/io.h>
+#include <linux/hw_bitfield.h>
 
 #define SYS_GRF_BASE		0x2600A000
 #define SYS_GRF_SOC_CON2	0x0008
@@ -21,6 +22,10 @@
 #define GPIO0B_PULL_L		0x0024
 #define GPIO0B_IE_L		0x002C
 
+#define TOP_IOC_BASE		0x26044000
+#define IOC_MISC_CON		0x00F0
+#define TOP_IOC_FORCE_JTAG	BIT(1)
+
 #define SYS_SGRF_BASE		0x26004000
 #define SYS_SGRF_SOC_CON14	0x0058
 #define SYS_SGRF_SOC_CON15	0x005C
@@ -190,6 +195,11 @@ int arch_cpu_init(void)
 	 */
 	writel(0xffffff00, SYS_SGRF_BASE + SYS_SGRF_SOC_CON20);
 
+	/* Disable JTAG exposed on SDMMC pins (GPIO2A2 and GPIO2A3) */
+	if (IS_ENABLED(CONFIG_ROCKCHIP_DISABLE_FORCE_JTAG))
+		writel(FIELD_PREP_WM16(TOP_IOC_FORCE_JTAG, 0),
+		       TOP_IOC_BASE + IOC_MISC_CON);
+
 	/* Disable USB3OTG0 U3 port, later enabled by USBDP PHY driver */
 	writel(0xffff0188, USB_GRF_BASE + USB3OTG0_CON1);
 

include/linux/hw_bitfield.h

@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2025, Collabora Ltd.
+ */
+
+#ifndef _LINUX_HW_BITFIELD_H
+#define _LINUX_HW_BITFIELD_H
+
+#include <linux/bitfield.h>
+#include <linux/build_bug.h>
+
+/**
+ * FIELD_PREP_WM16() - prepare a bitfield element with a mask in the upper half
+ * @_mask: shifted mask defining the field's length and position
+ * @_val:  value to put in the field
+ *
+ * FIELD_PREP_WM16() masks and shifts up the value, as well as bitwise ORs the
+ * result with the mask shifted up by 16.
+ *
+ * This is useful for a common design of hardware registers where the upper
+ * 16-bit half of a 32-bit register is used as a write-enable mask. In such a
+ * register, a bit in the lower half is only updated if the corresponding bit
+ * in the upper half is high.
+ */
+#define FIELD_PREP_WM16(_mask, _val)					     \
+	({								     \
+		typeof(_val) __val = _val;				     \
+		typeof(_mask) __mask = _mask;				     \
+		__BF_FIELD_CHECK(__mask, ((u16)0U), __val,		     \
+				 "HWORD_UPDATE: ");			     \
+		(((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) | \
+		((__mask) << 16);					     \
+	})
+
+/**
+ * FIELD_PREP_WM16_CONST() - prepare a constant bitfield element with a mask in
+ *                           the upper half
+ * @_mask: shifted mask defining the field's length and position
+ * @_val:  value to put in the field
+ *
+ * FIELD_PREP_WM16_CONST() masks and shifts up the value, as well as bitwise ORs
+ * the result with the mask shifted up by 16.
+ *
+ * This is useful for a common design of hardware registers where the upper
+ * 16-bit half of a 32-bit register is used as a write-enable mask. In such a
+ * register, a bit in the lower half is only updated if the corresponding bit
+ * in the upper half is high.
+ *
+ * Unlike FIELD_PREP_WM16(), this is a constant expression and can therefore
+ * be used in initializers. Error checking is less comfortable for this
+ * version.
+ */
+#define FIELD_PREP_WM16_CONST(_mask, _val)				 \
+	(								 \
+		FIELD_PREP_CONST(_mask, _val) |				 \
+		(BUILD_BUG_ON_ZERO((u64)(_mask) > U16_MAX) + \
+		 ((_mask) << 16))					 \
+	)
+
+
+#endif /* _LINUX_HW_BITFIELD_H */