From b91a0822d752a1d46ea9ad1ad0d28b93b16088f9 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 2 Mar 2023 02:46:32 +0100 Subject: [PATCH 01/11] mtd: spi-nor: Add CHIP_ERASE optimization Add support for CHIP_ERASE opcode 0xc7 . This is useful in case the entire SPI NOR is supposed to be erase at once, as is it considerably faster than 4k sector erase and even slightly faster than 64k block erase. The spi_nor_erase_chip() implementation is adapted from Linux 6.1.y as of commit 7d54cb2c26dad ("Linux 6.1.14") . The chip erase is only used in case the entire MTD device is being erased, and the chip does support this functionality. Timing figures from W25Q128JW: 16 MiB erase using 4kiB sector erase opcode 0x20 ... 107.5s 16 MiB erase using 64kiB block erase opcode 0xd8 ... 39.1s 16 MiB erase using chip erase opcode 0xc7 .......... 38.7s Signed-off-by: Marek Vasut Reviewed-by: Jagan Teki --- drivers/mtd/spi/spi-nor-core.c | 31 ++++++++++++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 2c3116ee530..83d7fe44ee1 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -903,6 +903,30 @@ static int read_bar(struct spi_nor *nor, const struct flash_info *info) } #endif +/** + * spi_nor_erase_chip() - Erase the entire flash memory. + * @nor: pointer to 'struct spi_nor'. + * + * Return: 0 on success, -errno otherwise. + */ +static int spi_nor_erase_chip(struct spi_nor *nor) +{ + struct spi_mem_op op = + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CHIP_ERASE, 0), + SPI_MEM_OP_NO_ADDR, + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_NO_DATA); + int ret; + + spi_nor_setup_op(nor, &op, nor->write_proto); + + ret = spi_mem_exec_op(nor->spi, &op); + if (ret) + return ret; + + return nor->mtd.size; +} + /* * Initiate the erasure of a single sector. Returns the number of bytes erased * on success, a negative error code on error. @@ -974,7 +998,12 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) if (ret < 0) goto erase_err; - ret = spi_nor_erase_sector(nor, addr); + if (len == mtd->size && + !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) { + ret = spi_nor_erase_chip(nor); + } else { + ret = spi_nor_erase_sector(nor, addr); + } if (ret < 0) goto erase_err; From 963b5da339a2ac8ad1451c9b84e746a2e26fd0d4 Mon Sep 17 00:00:00 2001 From: Dhruva Gole Date: Wed, 1 Mar 2023 13:13:45 +0530 Subject: [PATCH 02/11] spi: spi-mem: s/dummy/data buswidth check in dtr_supports_op() This should have been op->data.buswidth instead as we check for octal bus width for the data related ops Also add explanation for why there is checks for 8D even data bytes Cc: Pratyush Yadav Reviewed-by: Pratyush Yadav Tested-by: Nikhil M Jain Signed-off-by: Dhruva Gole Reviewed-by: Jagan Teki --- drivers/spi/spi-mem.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index 8e8995fc537..57a36f31a5d 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -181,8 +181,12 @@ bool spi_mem_dtr_supports_op(struct spi_slave *slave, if (op->dummy.nbytes && op->dummy.buswidth == 8 && op->dummy.nbytes % 2) return false; + /* + * Transactions of odd length do not make sense for 8D-8D-8D mode + * because a byte is transferred in just half a cycle. + */ if (op->data.dir != SPI_MEM_NO_DATA && - op->dummy.buswidth == 8 && op->data.nbytes % 2) + op->data.buswidth == 8 && op->data.nbytes % 2) return false; return spi_mem_check_buswidth(slave, op); From db58dc5438ec674cad438a606edc155d06914adc Mon Sep 17 00:00:00 2001 From: Dhruva Gole Date: Wed, 1 Mar 2023 13:13:46 +0530 Subject: [PATCH 03/11] spi: spi-mem: perform odd len check only while writing data in spi_mem_dtr_supports_op we have a check for allowing only even number of bytes to be r/w. Odd bytes writing can be a concern while writing data to a flash for example because 8 DTR mode doesn't support it. However, reading ODD Bytes even though may not be physically possible we can still allow for it because it will not have serious implications on any critical registers being overwritten since they are just reads. Cc: Vaishnav Achath Cc: Pratyush Yadav Cc: Vignesh Raghavendra Tested-by: Nikhil M Jain Signed-off-by: Dhruva Gole Reviewed-by: Jagan Teki --- drivers/spi/spi-mem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index 57a36f31a5d..b7eca583595 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -185,7 +185,7 @@ bool spi_mem_dtr_supports_op(struct spi_slave *slave, * Transactions of odd length do not make sense for 8D-8D-8D mode * because a byte is transferred in just half a cycle. */ - if (op->data.dir != SPI_MEM_NO_DATA && + if (op->data.dir != SPI_MEM_NO_DATA && op->data.dir != SPI_MEM_DATA_IN && op->data.buswidth == 8 && op->data.nbytes % 2) return false; From c008280a9a5db471cb8771812b98e3749017b54a Mon Sep 17 00:00:00 2001 From: Kunihiko Hayashi Date: Mon, 27 Mar 2023 14:34:51 +0900 Subject: [PATCH 04/11] spi: f-ospi: Add missing spi_mem_default_supports_op() helper The .supports_op() callback function returns true by default after performing driver-specific checks. Therefore the driver cannot apply the buswidth in devicetree. Call spi_mem_default_supports_op() helper to handle the buswidth in devicetree. Fixes: 358f803ae21c ("spi: Add Socionext F_OSPI SPI flash controller driver") Signed-off-by: Kunihiko Hayashi Reviewed-by: Jagan Teki --- drivers/spi/spi-sn-f-ospi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/spi-sn-f-ospi.c b/drivers/spi/spi-sn-f-ospi.c index ebf2903d3ea..e3633a52608 100644 --- a/drivers/spi/spi-sn-f-ospi.c +++ b/drivers/spi/spi-sn-f-ospi.c @@ -556,7 +556,7 @@ static bool f_ospi_supports_op(struct spi_slave *slave, if (!f_ospi_supports_op_width(op)) return false; - return true; + return spi_mem_default_supports_op(slave, op); } static int f_ospi_adjust_op_size(struct spi_slave *slave, struct spi_mem_op *op) From 0514227e19106ff15e0f42f24eedf2f1d8fce224 Mon Sep 17 00:00:00 2001 From: Jim Liu Date: Tue, 7 Mar 2023 16:10:35 +0800 Subject: [PATCH 05/11] spi: npcm-fiu: add regulator feature and remove set clock NPCM7xx/NPCM8xx default is boot from flash. removed set clock feature due to reliability and security. the clock will set by bootblock or tip. Signed-off-by: Jim Liu Reviewed-by: Jagan Teki --- drivers/spi/npcm_fiu_spi.c | 72 +++++++++++++++++++++++++++++++------- 1 file changed, 59 insertions(+), 13 deletions(-) diff --git a/drivers/spi/npcm_fiu_spi.c b/drivers/spi/npcm_fiu_spi.c index 7000fe5860d..73c506442ae 100644 --- a/drivers/spi/npcm_fiu_spi.c +++ b/drivers/spi/npcm_fiu_spi.c @@ -11,6 +11,7 @@ #include #include #include +#include #define DW_SIZE 4 #define CHUNK_SIZE 16 @@ -34,6 +35,34 @@ #define UMA_CTS_RDYST BIT(24) #define UMA_CTS_DEV_NUM_MASK GENMASK(9, 8) +/* Direct Write Configuration Register */ +#define DWR_CFG_WBURST_MASK GENMASK(25, 24) +#define DWR_CFG_ADDSIZ_MASK GENMASK(17, 16) +#define DWR_CFG_ABPCK_MASK GENMASK(11, 10) +#define DRW_CFG_DBPCK_MASK GENMASK(9, 8) +#define DRW_CFG_WRCMD 2 +enum { + DWR_WBURST_1_BYTE, + DWR_WBURST_16_BYTE = 3, +}; + +enum { + DWR_ADDSIZ_24_BIT, + DWR_ADDSIZ_32_BIT, +}; + +enum { + DWR_ABPCK_BIT_PER_CLK, + DWR_ABPCK_2_BIT_PER_CLK, + DWR_ABPCK_4_BIT_PER_CLK, +}; + +enum { + DWR_DBPCK_BIT_PER_CLK, + DWR_DBPCK_2_BIT_PER_CLK, + DWR_DBPCK_4_BIT_PER_CLK, +}; + struct npcm_fiu_regs { unsigned int drd_cfg; unsigned int dwr_cfg; @@ -67,19 +96,10 @@ struct npcm_fiu_regs { struct npcm_fiu_priv { struct npcm_fiu_regs *regs; - struct clk clk; }; static int npcm_fiu_spi_set_speed(struct udevice *bus, uint speed) { - struct npcm_fiu_priv *priv = dev_get_priv(bus); - int ret; - - debug("%s: set speed %u\n", bus->name, speed); - ret = clk_set_rate(&priv->clk, speed); - if (ret < 0) - return ret; - return 0; } @@ -349,13 +369,38 @@ static int npcm_fiu_exec_op(struct spi_slave *slave, static int npcm_fiu_spi_probe(struct udevice *bus) { struct npcm_fiu_priv *priv = dev_get_priv(bus); - int ret; + struct udevice *vqspi_supply; + int vqspi_uv; priv->regs = (struct npcm_fiu_regs *)dev_read_addr_ptr(bus); - ret = clk_get_by_index(bus, 0, &priv->clk); - if (ret < 0) - return ret; + if (IS_ENABLED(CONFIG_DM_REGULATOR)) { + device_get_supply_regulator(bus, "vqspi-supply", &vqspi_supply); + vqspi_uv = dev_read_u32_default(bus, "vqspi-microvolt", 0); + /* Set IO voltage */ + if (vqspi_supply && vqspi_uv) + regulator_set_value(vqspi_supply, vqspi_uv); + } + + return 0; +} + +static int npcm_fiu_spi_bind(struct udevice *bus) +{ + struct npcm_fiu_regs *regs; + + if (dev_read_bool(bus, "nuvoton,spix-mode")) { + regs = dev_read_addr_ptr(bus); + if (!regs) + return -EINVAL; + + /* Setup direct write cfg for SPIX */ + writel(FIELD_PREP(DWR_CFG_WBURST_MASK, DWR_WBURST_16_BYTE) | + FIELD_PREP(DWR_CFG_ADDSIZ_MASK, DWR_ADDSIZ_24_BIT) | + FIELD_PREP(DWR_CFG_ABPCK_MASK, DWR_ABPCK_4_BIT_PER_CLK) | + FIELD_PREP(DRW_CFG_DBPCK_MASK, DWR_DBPCK_4_BIT_PER_CLK) | + DRW_CFG_WRCMD, ®s->dwr_cfg); + } return 0; } @@ -384,4 +429,5 @@ U_BOOT_DRIVER(npcm_fiu_spi) = { .ops = &npcm_fiu_spi_ops, .priv_auto = sizeof(struct npcm_fiu_priv), .probe = npcm_fiu_spi_probe, + .bind = npcm_fiu_spi_bind, }; From 24c27b3c6ceab7295d12cd2ae0a47cfe9c136ecc Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sat, 1 Apr 2023 09:34:08 +0200 Subject: [PATCH 06/11] mtd: spi-nor: missing fallthrough in set_4byte() Add a missing fallthrough macro to avoid a -Wimplicit-fallthrough warning. Signed-off-by: Heinrich Schuchardt Reviewed-by: Jagan Teki --- drivers/mtd/spi/spi-nor-core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 83d7fe44ee1..f963ed026cc 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -669,6 +669,7 @@ static int set_4byte(struct spi_nor *nor, const struct flash_info *info, case SNOR_MFR_MICRON: /* Some Micron need WREN command; all will accept it */ need_wren = true; + fallthrough; case SNOR_MFR_ISSI: case SNOR_MFR_MACRONIX: case SNOR_MFR_WINBOND: From 8485595927e1685a8369426bda91b6a89dc2754c Mon Sep 17 00:00:00 2001 From: Ilias Apalodimas Date: Fri, 7 Apr 2023 12:13:00 +0300 Subject: [PATCH 07/11] spi: synquacer: Silence uninitialized variable warnings When building with clang, the compiler compains with drivers/spi/spi-synquacer.c:212:11: warning: variable 'bus_width' is used uninitialized whenever 'if' condition is false [-Wsometimes-uninitialized] else if (priv->mode & SPI_TX_OCTAL) ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/spi/spi-synquacer.c:276:11: note: uninitialized use occurs here val |= ((bus_width >> 1) << BUS_WIDTH); ^~~~~~~~~ drivers/spi/spi-synquacer.c:212:7: note: remove the 'if' if its condition is always true else if (priv->mode & SPI_TX_OCTAL) ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/spi/spi-synquacer.c:189:25: note: initialize the variable 'bus_width' to silence this warning So initialize bus_width to 1 and add a warning if none of the configured modes matches Signed-off-by: Ilias Apalodimas Acked-by: Jassi Brar Reviewed-by: Jagan Teki --- drivers/spi/spi-synquacer.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-synquacer.c b/drivers/spi/spi-synquacer.c index 0cae3dfc778..0f5d0a30c39 100644 --- a/drivers/spi/spi-synquacer.c +++ b/drivers/spi/spi-synquacer.c @@ -186,7 +186,7 @@ static void synquacer_spi_config(struct udevice *dev, void *rx, const void *tx) struct udevice *bus = dev->parent; struct synquacer_spi_priv *priv = dev_get_priv(bus); struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); - u32 val, div, bus_width; + u32 val, div, bus_width = 1; int rwflag; rwflag = (rx ? 1 : 0) | (tx ? 2 : 0); @@ -211,6 +211,8 @@ static void synquacer_spi_config(struct udevice *dev, void *rx, const void *tx) bus_width = 4; else if (priv->mode & SPI_TX_OCTAL) bus_width = 8; + else + log_warning("SPI mode not configured, setting to byte mode\n"); div = DIV_ROUND_UP(125000000, priv->speed); From 562d166a13ca88cb55ef4f4ddb016e27b7cb0d2e Mon Sep 17 00:00:00 2001 From: Takahiro Kuwano Date: Sun, 23 Apr 2023 01:55:49 +0200 Subject: [PATCH 08/11] mtd: spi-nor-core: Add fixups for s25fs512s This patch adds fixups for s25fs512s to address the following issues from reading SFDP: - Non-uniform sectors by factory default. The setting needs to be checked and assign erase hook as needed. - Page size is wrongly advertised in SFDP. - READ_1_1_2 (3Bh/3Ch), READ_1_1_4 (6Bh/6Ch), and PP_1_1_4 (32h/34h) are not supported. - Bank Address Register (BAR) is not supported. In addition, volatile version of Quad Enable is used for safety. Based on patch by Takahiro Kuwano with s25fs_s_post_bfpt_fixup() updated to use 4-byte address commands instead of extended address mode and the page_size is fixed to 256 For future use, manufacturer code should be moved out from framework code as same as in Linux. Reviewed-by: Marek Vasut Signed-off-by: Takahiro Kuwano Signed-off-by: Hai Pham Signed-off-by: Cong Dang Signed-off-by: Marek Vasut Reviewed-by: Jagan Teki --- drivers/mtd/spi/spi-nor-core.c | 85 ++++++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index f963ed026cc..6093277f171 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -3229,6 +3229,87 @@ static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info, /* Use ID byte 4 to distinguish S25FS256T and S25Hx-T */ #define S25FS256T_ID4 (0x08) +/* Number of dummy cycle for Read Any Register (RDAR) op. */ +#define S25FS_S_RDAR_DUMMY 8 + +static int s25fs_s_quad_enable(struct spi_nor *nor) +{ + return spansion_quad_enable_volatile(nor, 0, S25FS_S_RDAR_DUMMY); +} + +static int s25fs_s_erase_non_uniform(struct spi_nor *nor, loff_t addr) +{ + /* Support 8 x 4KB sectors at bottom */ + return spansion_erase_non_uniform(nor, addr, SPINOR_OP_BE_4K_4B, 0, SZ_32K); +} + +static int s25fs_s_setup(struct spi_nor *nor, const struct flash_info *info, + const struct spi_nor_flash_parameter *params) +{ + int ret; + u8 cfr3v; + + /* Bank Address Register is not supported */ + if (CONFIG_IS_ENABLED(SPI_FLASH_BAR)) + return -EOPNOTSUPP; + + /* + * Read CR3V to check if uniform sector is selected. If not, assign an + * erase hook that supports non-uniform erase. + */ + ret = spansion_read_any_reg(nor, SPINOR_REG_ADDR_CFR3V, + S25FS_S_RDAR_DUMMY, &cfr3v); + if (ret) + return ret; + if (!(cfr3v & CFR3V_UNHYSA)) + nor->erase = s25fs_s_erase_non_uniform; + + return spi_nor_default_setup(nor, info, params); +} + +static void s25fs_s_default_init(struct spi_nor *nor) +{ + nor->setup = s25fs_s_setup; +} + +static int s25fs_s_post_bfpt_fixup(struct spi_nor *nor, + const struct sfdp_parameter_header *header, + const struct sfdp_bfpt *bfpt, + struct spi_nor_flash_parameter *params) +{ + /* The erase size is set to 4K from BFPT, but it's wrong. Fix it. */ + nor->erase_opcode = SPINOR_OP_SE; + nor->mtd.erasesize = nor->info->sector_size; + + /* The S25FS-S chip family reports 512-byte pages in BFPT but + * in reality the write buffer still wraps at the safe default + * of 256 bytes. Overwrite the page size advertised by BFPT + * to get the writes working. + */ + params->page_size = 256; + + return 0; +} + +static void s25fs_s_post_sfdp_fixup(struct spi_nor *nor, + struct spi_nor_flash_parameter *params) +{ + /* READ_1_1_2 is not supported */ + params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_2; + /* READ_1_1_4 is not supported */ + params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_4; + /* PP_1_1_4 is not supported */ + params->hwcaps.mask &= ~SNOR_HWCAPS_PP_1_1_4; + /* Use volatile register to enable quad */ + params->quad_enable = s25fs_s_quad_enable; +} + +static struct spi_nor_fixups s25fs_s_fixups = { + .default_init = s25fs_s_default_init, + .post_bfpt = s25fs_s_post_bfpt_fixup, + .post_sfdp = s25fs_s_post_sfdp_fixup, +}; + static int s25_mdp_ready(struct spi_nor *nor) { u32 addr; @@ -3927,6 +4008,10 @@ void spi_nor_set_fixups(struct spi_nor *nor) if (CONFIG_IS_ENABLED(SPI_FLASH_BAR) && !strcmp(nor->info->name, "s25fl256l")) nor->fixups = &s25fl256l_fixups; + + /* For FS-S (family ID = 0x81) */ + if (JEDEC_MFR(nor->info) == SNOR_MFR_SPANSION && nor->info->id[5] == 0x81) + nor->fixups = &s25fs_s_fixups; #endif #ifdef CONFIG_SPI_FLASH_MT35XU From 44e2de0480a8a5a5780b6b200935a96b961b94e7 Mon Sep 17 00:00:00 2001 From: Apurva Nandan Date: Wed, 12 Apr 2023 16:28:54 +0530 Subject: [PATCH 09/11] spi: cadence-quadspi: Fix check condition for DTR ops buswidth and dtr fields in spi_mem_op are only valid when the corresponding spi_mem_op phase has a non-zero length. For example, SPI NAND core doesn't set buswidth when using SPI_MEM_OP_NO_ADDR phase. Fix the dtr checks in set_protocol() to ignore empty spi_mem_op phases, as checking for dtr field in empty phase will result in false negatives. Signed-off-by: Apurva Nandan Signed-off-by: Dhruva Gole Reviewed-by: Jagan Teki --- drivers/spi/cadence_qspi.c | 11 +++++++++-- drivers/spi/cadence_qspi_apb.c | 11 ++++++++++- 2 files changed, 19 insertions(+), 3 deletions(-) diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index c7f10c50132..a858a62888e 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -362,8 +362,15 @@ static bool cadence_spi_mem_supports_op(struct spi_slave *slave, { bool all_true, all_false; - all_true = op->cmd.dtr && op->addr.dtr && op->dummy.dtr && - op->data.dtr; + /* + * op->dummy.dtr is required for converting nbytes into ncycles. + * Also, don't check the dtr field of the op phase having zero nbytes. + */ + all_true = op->cmd.dtr && + (!op->addr.nbytes || op->addr.dtr) && + (!op->dummy.nbytes || op->dummy.dtr) && + (!op->data.nbytes || op->data.dtr); + all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr && !op->data.dtr; diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 21fe2e655c5..dfcdeff8054 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -120,7 +120,16 @@ static int cadence_qspi_set_protocol(struct cadence_spi_priv *priv, { int ret; - priv->dtr = op->data.dtr && op->cmd.dtr && op->addr.dtr; + /* + * For an op to be DTR, cmd phase along with every other non-empty + * phase should have dtr field set to 1. If an op phase has zero + * nbytes, ignore its dtr field; otherwise, check its dtr field. + * Also, dummy checks not performed here Since supports_op() + * already checks that all or none of the fields are DTR. + */ + priv->dtr = op->cmd.dtr && + (!op->addr.nbytes || op->addr.dtr) && + (!op->data.nbytes || op->data.dtr); ret = cadence_qspi_buswidth_to_inst_type(op->cmd.buswidth); if (ret < 0) From 8077d296adff235e13c1478f92ef42c08e17ec33 Mon Sep 17 00:00:00 2001 From: Apurva Nandan Date: Wed, 12 Apr 2023 16:28:55 +0530 Subject: [PATCH 10/11] spi: cadence-quadspi: Use STIG mode for all ops with small payload OSPI controller supports all types of op variants in STIG mode, only limitation being that the data payload should be less than 8 bytes when not using memory banks. STIG mode is more stable for operations that send small data payload and is more efficient than using DMA for few bytes of memory accesses. It overcomes the limitation of minimum 4 bytes read from flash into RAM seen in DAC mode. Use STIG mode for all read and write operations that require data input/output of less than 8 bytes from the flash, and thereby support all four phases, cmd/address/dummy/data, through OSPI STIG. Also, remove the reorder address chunk in apb_command_write since we now setup ADDR BIT field that does the same job in a cleaner way. Signed-off-by: Apurva Nandan Signed-off-by: Dhruva Gole Acked-by: Jagan Teki --- drivers/spi/cadence_qspi.c | 5 ++-- drivers/spi/cadence_qspi_apb.c | 42 ++++++++++++++++++---------------- 2 files changed, 24 insertions(+), 23 deletions(-) diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index a858a62888e..f931e4cf3e2 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -312,13 +312,12 @@ static int cadence_spi_mem_exec_op(struct spi_slave *spi, * which is unsupported on some flash devices during register * reads, prefer STIG mode for such small reads. */ - if (!op->addr.nbytes || - op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX) + if (op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX) mode = CQSPI_STIG_READ; else mode = CQSPI_READ; } else { - if (!op->addr.nbytes || !op->data.buf.out) + if (op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX) mode = CQSPI_STIG_WRITE; else mode = CQSPI_WRITE; diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index dfcdeff8054..4c055a05807 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -462,11 +462,6 @@ int cadence_qspi_apb_command_read(struct cadence_spi_priv *priv, unsigned int dummy_clk; u8 opcode; - if (rxlen > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) { - printf("QSPI: Invalid input arguments rxlen %u\n", rxlen); - return -EINVAL; - } - if (priv->dtr) opcode = op->cmd.opcode >> 8; else @@ -549,26 +544,12 @@ int cadence_qspi_apb_command_write(struct cadence_spi_priv *priv, unsigned int reg = 0; unsigned int wr_data; unsigned int wr_len; + unsigned int dummy_clk; unsigned int txlen = op->data.nbytes; const void *txbuf = op->data.buf.out; void *reg_base = priv->regbase; - u32 addr; u8 opcode; - /* Reorder address to SPI bus order if only transferring address */ - if (!txlen) { - addr = cpu_to_be32(op->addr.val); - if (op->addr.nbytes == 3) - addr >>= 8; - txbuf = &addr; - txlen = op->addr.nbytes; - } - - if (txlen > CQSPI_STIG_DATA_LEN_MAX) { - printf("QSPI: Invalid input arguments txlen %u\n", txlen); - return -EINVAL; - } - if (priv->dtr) opcode = op->cmd.opcode >> 8; else @@ -576,6 +557,27 @@ int cadence_qspi_apb_command_write(struct cadence_spi_priv *priv, reg |= opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; + /* setup ADDR BIT field */ + if (op->addr.nbytes) { + writel(op->addr.val, priv->regbase + CQSPI_REG_CMDADDRESS); + /* + * address bytes are zero indexed + */ + reg |= (((op->addr.nbytes - 1) & + CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) << + CQSPI_REG_CMDCTRL_ADD_BYTES_LSB); + reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB); + } + + /* Set up dummy cycles. */ + dummy_clk = cadence_qspi_calc_dummy(op, priv->dtr); + if (dummy_clk > CQSPI_DUMMY_CLKS_MAX) + return -EOPNOTSUPP; + + if (dummy_clk) + reg |= (dummy_clk & CQSPI_REG_CMDCTRL_DUMMY_MASK) + << CQSPI_REG_CMDCTRL_DUMMY_LSB; + if (txlen) { /* writing data = yes */ reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB); From 08b3098eadc7f826c3e6fb9d184cf6d82f5028fe Mon Sep 17 00:00:00 2001 From: Dhruva Gole Date: Wed, 12 Apr 2023 16:28:56 +0530 Subject: [PATCH 11/11] spi: cadence-quadspi: Reset CMD_CTRL Reg on cmd r/w completion If one leaves the CQSPI_REG_CMDCTRL in an unclean state this may cause issues in future command reads. This issue came to light when some flash reads in STIG mode were coming back dirty. Co-developed-by: Apurva Nandan Signed-off-by: Apurva Nandan Signed-off-by: Dhruva Gole Acked-by: Jagan Teki --- drivers/spi/cadence_qspi_apb.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 4c055a05807..9ce2c0f254f 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -376,6 +376,9 @@ int cadence_qspi_apb_exec_flash_cmd(void *reg_base, unsigned int reg) if (!cadence_qspi_wait_idle(reg_base)) return -EIO; + /* Flush the CMDCTRL reg after the execution */ + writel(0, reg_base + CQSPI_REG_CMDCTRL); + return 0; }