diff --git a/arch/arm/dts/mt7981.dtsi b/arch/arm/dts/mt7981.dtsi
index fc13b90caf6..b3f8a50cd10 100644
--- a/arch/arm/dts/mt7981.dtsi
+++ b/arch/arm/dts/mt7981.dtsi
@@ -144,8 +144,7 @@
 			 <&infracfg_ao CK_INFRA_PWM_BSEL>,
 			 <&infracfg_ao CK_INFRA_PWM1_CK>,
 			 <&infracfg_ao CK_INFRA_PWM2_CK>,
-			 /* FIXME */
-			 <&infracfg_ao CK_INFRA_PWM2_CK>;
+			 <&infracfg_ao CK_INFRA_PWM3_CK>;
 		assigned-clocks = <&topckgen CK_TOP_PWM_SEL>;
 		assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>;
 		clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
diff --git a/drivers/clk/mediatek/clk-mt7981.c b/drivers/clk/mediatek/clk-mt7981.c
index 4435430dcde..7b692186dc1 100644
--- a/drivers/clk/mediatek/clk-mt7981.c
+++ b/drivers/clk/mediatek/clk-mt7981.c
@@ -381,6 +381,8 @@ static const struct mtk_composite infra_muxes[] = {
 		  9, 1),
 	INFRA_MUX(CK_INFRA_PWM2_SEL, "infra_pwm2_sel", infra_pwm1_parents, 0x10,
 		  11, 1),
+	INFRA_MUX(CK_INFRA_PWM3_SEL, "infra_pwm3_sel", infra_pwm1_parents, 0x10,
+		  15, 1),
 	INFRA_MUX(CK_INFRA_PWM_BSEL, "infra_pwm_bsel", infra_pwm_bsel_parents,
 		  0x10, 13, 2),
 	INFRA_MUX(CK_INFRA_PCIE_SEL, "infra_pcie_sel", infra_pcie_parents, 0x20,
@@ -445,6 +447,7 @@ static const struct mtk_gate infracfg_ao_gates[] = {
 	GATE_INFRA0_INFRA(CK_INFRA_PWM_STA, "infra_pwm_sta", CK_INFRA_PWM_BSEL, 2),
 	GATE_INFRA0_INFRA(CK_INFRA_PWM1_CK, "infra_pwm1", CK_INFRA_PWM1_SEL, 3),
 	GATE_INFRA0_INFRA(CK_INFRA_PWM2_CK, "infra_pwm2", CK_INFRA_PWM2_SEL, 4),
+	GATE_INFRA0_INFRA(CK_INFRA_PWM3_CK, "infra_pwm3", CK_INFRA_PWM3_SEL, 27),
 	GATE_INFRA0_TOP(CK_INFRA_CQ_DMA_CK, "infra_cq_dma", CK_TOP_SYSAXI, 6),
 	GATE_INFRA0_TOP(CK_INFRA_AUD_BUS_CK, "infra_aud_bus", CK_TOP_SYSAXI, 8),
 	GATE_INFRA0_TOP(CK_INFRA_AUD_26M_CK, "infra_aud_26m", CK_TOP_F26M_SEL, 9),