Merge tag 'xilinx-for-v2026.04-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next

AMD/Xilinx/FPGA changes for v2026.04-rc1

xilinx:
- Sync ESRT with detected GUID
- DT cleanups
- Add logic for FRU information multiple times
- Enable more drivers pca9541, usb5744
- Enable more commands
- Cleanup firmware DT bindings

firmware:
- Add enhancement SMC format support

clk/versal:
- Various cleanups
- Add support for Versal Gen 2

i2c:
- cdns: Add timeout for RXDV status bit polling

spi:
- cadence: Remove cdns,is-dma DT property
- cadence: Remove duplicated return
- cadence_versal: Update flash reset delay

memtop:
- Update max memory reserved spaces to 64

Versal Gen 2:
- Aligned addresses with default memory map
- Add support for reading multiboot value

MB-V:
- Make SPL smaller
- Add support for SPI
- Move SPL to run out of BRAM

ZynqMP:
- Change default load address for BL32

include/dt-bindings/power/xlnx-versal-power.h

@@ -1,54 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- *  Copyright (C) 2019 - 2021 Xilinx, Inc.
- */
-
-#ifndef _DT_BINDINGS_VERSAL_POWER_H
-#define _DT_BINDINGS_VERSAL_POWER_H
-
-#define PM_DEV_RPU0_0				(0x18110005U)
-#define PM_DEV_RPU0_1				(0x18110006U)
-#define PM_DEV_OCM_0				(0x18314007U)
-#define PM_DEV_OCM_1				(0x18314008U)
-#define PM_DEV_OCM_2				(0x18314009U)
-#define PM_DEV_OCM_3				(0x1831400aU)
-#define PM_DEV_TCM_0_A				(0x1831800bU)
-#define PM_DEV_TCM_0_B				(0x1831800cU)
-#define PM_DEV_TCM_1_A				(0x1831800dU)
-#define PM_DEV_TCM_1_B				(0x1831800eU)
-#define PM_DEV_USB_0				(0x18224018U)
-#define PM_DEV_GEM_0				(0x18224019U)
-#define PM_DEV_GEM_1				(0x1822401aU)
-#define PM_DEV_SPI_0				(0x1822401bU)
-#define PM_DEV_SPI_1				(0x1822401cU)
-#define PM_DEV_I2C_0				(0x1822401dU)
-#define PM_DEV_I2C_1				(0x1822401eU)
-#define PM_DEV_CAN_FD_0				(0x1822401fU)
-#define PM_DEV_CAN_FD_1				(0x18224020U)
-#define PM_DEV_UART_0				(0x18224021U)
-#define PM_DEV_UART_1				(0x18224022U)
-#define PM_DEV_GPIO				(0x18224023U)
-#define PM_DEV_TTC_0				(0x18224024U)
-#define PM_DEV_TTC_1				(0x18224025U)
-#define PM_DEV_TTC_2				(0x18224026U)
-#define PM_DEV_TTC_3				(0x18224027U)
-#define PM_DEV_SWDT_FPD				(0x18224029U)
-#define PM_DEV_OSPI				(0x1822402aU)
-#define PM_DEV_QSPI				(0x1822402bU)
-#define PM_DEV_GPIO_PMC				(0x1822402cU)
-#define PM_DEV_I2C_PMC				(0x1822402dU)
-#define PM_DEV_SDIO_0				(0x1822402eU)
-#define PM_DEV_SDIO_1				(0x1822402fU)
-#define PM_DEV_RTC				(0x18224034U)
-#define PM_DEV_ADMA_0				(0x18224035U)
-#define PM_DEV_ADMA_1				(0x18224036U)
-#define PM_DEV_ADMA_2				(0x18224037U)
-#define PM_DEV_ADMA_3				(0x18224038U)
-#define PM_DEV_ADMA_4				(0x18224039U)
-#define PM_DEV_ADMA_5				(0x1822403aU)
-#define PM_DEV_ADMA_6				(0x1822403bU)
-#define PM_DEV_ADMA_7				(0x1822403cU)
-#define PM_DEV_AMS_ROOT				(0x18224055U)
-#define PM_DEV_AI				(0x18224072U)
-
-#endif

include/zynqmp_firmware.h

@@ -521,4 +521,12 @@ typedef int (*smc_call_handler_t)(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
 
 extern smc_call_handler_t __data smc_call_handler;
 
+#define PM_MODULE_ID		2
+
+#define PASS_THROUGH_FW_CMD_ID	GENMASK(11, 0)
+#define PLM_MODULE_ID_MASK	GENMASK(15, 8)
+#define API_ID_MASK		GENMASK(7, 0)
+
+#define PM_DEV_OSPI		(0x1822402aU)
+
 #endif /* _ZYNQMP_FIRMWARE_H_ */