diff --git a/MAINTAINERS b/MAINTAINERS index 899f26b4d8c..53034b703df 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -418,6 +418,7 @@ R: GSS_MTK_Uboot_upstream T: git https://git.u-boot-project.org/u-boot/custodians/u-boot-mediatek.git S: Maintained F: arch/arm/dts/mt* +F: drivers/power/domain/mt* F: drivers/power/regulator/mt*.c F: drivers/usb/mtu3/ F: include/power/mt*.h diff --git a/configs/mt7622_rfb_defconfig b/configs/mt7622_rfb_defconfig index b3b688ff825..10df7847a4b 100644 --- a/configs/mt7622_rfb_defconfig +++ b/configs/mt7622_rfb_defconfig @@ -51,7 +51,7 @@ CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_PINCTRL_MT7622=y CONFIG_POWER_DOMAIN=y -CONFIG_MTK_POWER_DOMAIN=y +CONFIG_MT7622_POWER_DOMAIN=y CONFIG_RAM=y CONFIG_DM_SERIAL=y CONFIG_MTK_SERIAL=y diff --git a/configs/mt7623a_unielec_u7623_02_defconfig b/configs/mt7623a_unielec_u7623_02_defconfig index 826f49a9626..77473e2731f 100644 --- a/configs/mt7623a_unielec_u7623_02_defconfig +++ b/configs/mt7623a_unielec_u7623_02_defconfig @@ -49,7 +49,7 @@ CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_PINCTRL_MT7623=y CONFIG_POWER_DOMAIN=y -CONFIG_MTK_POWER_DOMAIN=y +CONFIG_MT2701_POWER_DOMAIN=y CONFIG_DM_SERIAL=y CONFIG_MTK_SERIAL=y CONFIG_SYSRESET=y diff --git a/configs/mt7623n_bpir2_defconfig b/configs/mt7623n_bpir2_defconfig index aeef3bebe96..aacaf5380fa 100644 --- a/configs/mt7623n_bpir2_defconfig +++ b/configs/mt7623n_bpir2_defconfig @@ -51,7 +51,7 @@ CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_PINCTRL_MT7623=y CONFIG_POWER_DOMAIN=y -CONFIG_MTK_POWER_DOMAIN=y +CONFIG_MT2701_POWER_DOMAIN=y CONFIG_DM_SERIAL=y CONFIG_MTK_SERIAL=y CONFIG_SYSRESET=y diff --git a/configs/mt7629_rfb_defconfig b/configs/mt7629_rfb_defconfig index 72b1c83312e..91da684939a 100644 --- a/configs/mt7629_rfb_defconfig +++ b/configs/mt7629_rfb_defconfig @@ -83,7 +83,7 @@ CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_PINCTRL_MT7629=y CONFIG_POWER_DOMAIN=y -CONFIG_MTK_POWER_DOMAIN=y +CONFIG_MT7622_POWER_DOMAIN=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_RAM=y diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig index a96c3fb979c..0cadd9b93a9 100644 --- a/drivers/power/domain/Kconfig +++ b/drivers/power/domain/Kconfig @@ -83,12 +83,29 @@ config MESON_SECURE_POWER_DOMAIN Enable support for manipulating Amlogic Meson Secure power domains. Support for Amlogic A1 series. -config MTK_POWER_DOMAIN - bool "Enable the MediaTek power domain driver" +config MT2701_POWER_DOMAIN + bool "Enable the MediaTek power domain driver for MT2701 compatible SoC" depends on POWER_DOMAIN && ARCH_MEDIATEK + select MTK_POWER_DOMAIN help Enable support for manipulating MediaTek power domains via MMIO - mapped registers. + mapped registers for MT2701 compatible SoC. The driver powers + the SoC power domains on and off and handles the associated bus + protection bits. It is also used on MT7623. + +config MT7622_POWER_DOMAIN + bool "Enable the MediaTek power domain driver for MT7622 compatible SoC" + depends on POWER_DOMAIN && ARCH_MEDIATEK + select MTK_POWER_DOMAIN + help + Enable support for manipulating MediaTek power domains via MMIO + mapped registers for MT7622 compatible SoC. The driver powers + the SoC power domains on and off and handles the associated bus + protection bits. It is also used on MT7629. + +config MTK_POWER_DOMAIN + bool + depends on POWER_DOMAIN && ARCH_MEDIATEK config QCOM_RPMH_POWER_DOMAIN bool "Enable the QCOM RPMH Power domain driver" diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile index f3cce2b104e..66772b5d346 100644 --- a/drivers/power/domain/Makefile +++ b/drivers/power/domain/Makefile @@ -14,6 +14,8 @@ obj-$(CONFIG_IMX8MP_MEDIAMIX_BLKCTRL) += imx8mp-mediamix.o obj-$(CONFIG_MESON_EE_POWER_DOMAIN) += meson-ee-pwrc.o obj-$(CONFIG_MESON_GX_VPU_POWER_DOMAIN) += meson-gx-pwrc-vpu.o obj-$(CONFIG_MESON_SECURE_POWER_DOMAIN) += meson-secure-pwrc.o +obj-$(CONFIG_MT2701_POWER_DOMAIN) += mt2701-power-domain.o +obj-$(CONFIG_MT7622_POWER_DOMAIN) += mt7622-power-domain.o obj-$(CONFIG_MTK_POWER_DOMAIN) += mtk-power-domain.o obj-$(CONFIG_QCOM_RPMH_POWER_DOMAIN) += qcom-rpmhpd.o obj-$(CONFIG_RENESAS_R8A78000_POWER_DOMAIN) += renesas-r8a78000-power-domain.o diff --git a/drivers/power/domain/mt2701-power-domain.c b/drivers/power/domain/mt2701-power-domain.c new file mode 100644 index 00000000000..5626235360e --- /dev/null +++ b/drivers/power/domain/mt2701-power-domain.c @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 MediaTek Inc. + * Copyright (C) 2026 BayLibre, SAS + * Author: Ryder Lee + * Julien Stephan + */ + +#include +#include +#include + +#include "mtk-power-domain.h" + +static const struct mtk_scp_domain_data mt2701_scp_domain[] = { + [MT2701_POWER_DOMAIN_CONN] = { + .sta_mask = PWR_STATUS_CONN, + .ctl_offs = SPM_CONN_PWR_CON, + .bus_prot_mask = BIT(8) | BIT(2), + }, + [MT2701_POWER_DOMAIN_DISP] = { + .sta_mask = PWR_STATUS_DISP, + .ctl_offs = SPM_DIS_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + .bus_prot_mask = BIT(2), + }, + [MT2701_POWER_DOMAIN_MFG] = { + .sta_mask = PWR_STATUS_MFG, + .ctl_offs = SPM_MFG_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, + [MT2701_POWER_DOMAIN_VDEC] = { + .sta_mask = PWR_STATUS_VDEC, + .ctl_offs = SPM_VDE_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, + [MT2701_POWER_DOMAIN_ISP] = { + .sta_mask = PWR_STATUS_ISP, + .ctl_offs = SPM_ISP_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(13, 12), + }, + [MT2701_POWER_DOMAIN_BDP] = { + .sta_mask = PWR_STATUS_BDP, + .ctl_offs = SPM_BDP_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + }, + [MT2701_POWER_DOMAIN_ETH] = { + .sta_mask = PWR_STATUS_ETH, + .ctl_offs = SPM_ETH_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(15, 12), + }, + [MT2701_POWER_DOMAIN_HIF] = { + .sta_mask = PWR_STATUS_HIF, + .ctl_offs = SPM_HIF_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(15, 12), + }, + [MT2701_POWER_DOMAIN_IFR_MSC] = { + .sta_mask = PWR_STATUS_IFR_MSC, + .ctl_offs = SPM_IFR_MSC_PWR_CON, + }, +}; + +static const struct udevice_id mt2701_power_domain_ids[] = { + { + .compatible = "mediatek,mt2701-scpsys", + .data = (ulong)&mt2701_scp_domain, + }, + { + .compatible = "mediatek,mt7623-scpsys", + .data = (ulong)&mt2701_scp_domain, + }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(mt2701_power_domain) = { + .name = "mt2701_power_domain", + .id = UCLASS_POWER_DOMAIN, + .ops = &mtk_power_domain_ops, + .probe = mtk_power_domain_probe, + .of_match = mt2701_power_domain_ids, + .priv_auto = sizeof(struct mtk_scp_domain), +}; diff --git a/drivers/power/domain/mt7622-power-domain.c b/drivers/power/domain/mt7622-power-domain.c new file mode 100644 index 00000000000..487ae477bb0 --- /dev/null +++ b/drivers/power/domain/mt7622-power-domain.c @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 MediaTek Inc. + * Copyright (C) 2026 BayLibre, SAS + * Author: Ryder Lee + * Julien Stephan + */ + +#include +#include +#include + +#include "mtk-power-domain.h" + +static const struct mtk_scp_domain_data mt7622_scp_domain[] = { + [MT7622_POWER_DOMAIN_ETHSYS] = { + .sta_mask = PWR_STATUS_ETHSYS, + .ctl_offs = SPM_ETHSYS_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(15, 12), + .bus_prot_mask = (BIT(3) | BIT(17)), + }, + [MT7622_POWER_DOMAIN_HIF0] = { + .sta_mask = PWR_STATUS_HIF0, + .ctl_offs = SPM_HIF0_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(15, 12), + .bus_prot_mask = GENMASK(25, 24), + }, + [MT7622_POWER_DOMAIN_HIF1] = { + .sta_mask = PWR_STATUS_HIF1, + .ctl_offs = SPM_HIF1_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(15, 12), + .bus_prot_mask = GENMASK(28, 26), + }, +}; + +static const struct udevice_id mt7622_power_domain_ids[] = { + { + .compatible = "mediatek,mt7622-scpsys", + .data = (ulong)&mt7622_scp_domain, + }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(mt7622_power_domain) = { + .name = "mt7622_power_domain", + .id = UCLASS_POWER_DOMAIN, + .ops = &mtk_power_domain_ops, + .probe = mtk_power_domain_probe, + .of_match = mt7622_power_domain_ids, + .priv_auto = sizeof(struct mtk_scp_domain), +}; diff --git a/drivers/power/domain/mtk-power-domain.c b/drivers/power/domain/mtk-power-domain.c index 18a45a131b8..a8045c1f91e 100644 --- a/drivers/power/domain/mtk-power-domain.c +++ b/drivers/power/domain/mtk-power-domain.c @@ -6,153 +6,13 @@ #include #include -#include -#include #include #include #include -#include -#include #include #include -#include -#include - -#define SPM_EN (0xb16 << 16 | 0x1) -#define SPM_VDE_PWR_CON 0x0210 -#define SPM_MFG_PWR_CON 0x0214 -#define SPM_ISP_PWR_CON 0x0238 -#define SPM_DIS_PWR_CON 0x023c -#define SPM_CONN_PWR_CON 0x0280 -#define SPM_BDP_PWR_CON 0x029c -#define SPM_ETH_PWR_CON 0x02a0 -#define SPM_HIF_PWR_CON 0x02a4 -#define SPM_IFR_MSC_PWR_CON 0x02a8 -#define SPM_ETHSYS_PWR_CON 0x2e0 -#define SPM_HIF0_PWR_CON 0x2e4 -#define SPM_HIF1_PWR_CON 0x2e8 -#define SPM_PWR_STATUS 0x60c -#define SPM_PWR_STATUS_2ND 0x610 - -#define PWR_RST_B_BIT BIT(0) -#define PWR_ISO_BIT BIT(1) -#define PWR_ON_BIT BIT(2) -#define PWR_ON_2ND_BIT BIT(3) -#define PWR_CLK_DIS_BIT BIT(4) - -#define PWR_STATUS_CONN BIT(1) -#define PWR_STATUS_DISP BIT(3) -#define PWR_STATUS_MFG BIT(4) -#define PWR_STATUS_ISP BIT(5) -#define PWR_STATUS_VDEC BIT(7) -#define PWR_STATUS_BDP BIT(14) -#define PWR_STATUS_ETH BIT(15) -#define PWR_STATUS_HIF BIT(16) -#define PWR_STATUS_IFR_MSC BIT(17) -#define PWR_STATUS_ETHSYS BIT(24) -#define PWR_STATUS_HIF0 BIT(25) -#define PWR_STATUS_HIF1 BIT(26) - -/* Infrasys configuration */ -#define INFRA_TOPDCM_CTRL 0x10 -#define INFRA_TOPAXI_PROT_EN 0x220 -#define INFRA_TOPAXI_PROT_STA1 0x228 - -#define DCM_TOP_EN BIT(0) - -struct mtk_scp_domain; - -struct mtk_scp_domain_data { - u32 sta_mask; - int ctl_offs; - u32 sram_pdn_bits; - u32 sram_pdn_ack_bits; - u32 bus_prot_mask; -}; - -struct mtk_scp_domain { - void __iomem *base; - void __iomem *infracfg; - const struct mtk_scp_domain_data *data; -}; - -static const struct mtk_scp_domain_data scp_domain_mt2701[] = { - [MT2701_POWER_DOMAIN_CONN] = { - .sta_mask = PWR_STATUS_CONN, - .ctl_offs = SPM_CONN_PWR_CON, - .bus_prot_mask = BIT(8) | BIT(2), - }, - [MT2701_POWER_DOMAIN_DISP] = { - .sta_mask = PWR_STATUS_DISP, - .ctl_offs = SPM_DIS_PWR_CON, - .sram_pdn_bits = GENMASK(11, 8), - .bus_prot_mask = BIT(2), - }, - [MT2701_POWER_DOMAIN_MFG] = { - .sta_mask = PWR_STATUS_MFG, - .ctl_offs = SPM_MFG_PWR_CON, - .sram_pdn_bits = GENMASK(11, 8), - .sram_pdn_ack_bits = GENMASK(12, 12), - }, - [MT2701_POWER_DOMAIN_VDEC] = { - .sta_mask = PWR_STATUS_VDEC, - .ctl_offs = SPM_VDE_PWR_CON, - .sram_pdn_bits = GENMASK(11, 8), - .sram_pdn_ack_bits = GENMASK(12, 12), - }, - [MT2701_POWER_DOMAIN_ISP] = { - .sta_mask = PWR_STATUS_ISP, - .ctl_offs = SPM_ISP_PWR_CON, - .sram_pdn_bits = GENMASK(11, 8), - .sram_pdn_ack_bits = GENMASK(13, 12), - }, - [MT2701_POWER_DOMAIN_BDP] = { - .sta_mask = PWR_STATUS_BDP, - .ctl_offs = SPM_BDP_PWR_CON, - .sram_pdn_bits = GENMASK(11, 8), - }, - [MT2701_POWER_DOMAIN_ETH] = { - .sta_mask = PWR_STATUS_ETH, - .ctl_offs = SPM_ETH_PWR_CON, - .sram_pdn_bits = GENMASK(11, 8), - .sram_pdn_ack_bits = GENMASK(15, 12), - }, - [MT2701_POWER_DOMAIN_HIF] = { - .sta_mask = PWR_STATUS_HIF, - .ctl_offs = SPM_HIF_PWR_CON, - .sram_pdn_bits = GENMASK(11, 8), - .sram_pdn_ack_bits = GENMASK(15, 12), - }, - [MT2701_POWER_DOMAIN_IFR_MSC] = { - .sta_mask = PWR_STATUS_IFR_MSC, - .ctl_offs = SPM_IFR_MSC_PWR_CON, - }, -}; - -static const struct mtk_scp_domain_data scp_domain_mt7622[] = { - [MT7622_POWER_DOMAIN_ETHSYS] = { - .sta_mask = PWR_STATUS_ETHSYS, - .ctl_offs = SPM_ETHSYS_PWR_CON, - .sram_pdn_bits = GENMASK(11, 8), - .sram_pdn_ack_bits = GENMASK(15, 12), - .bus_prot_mask = (BIT(3) | BIT(17)), - }, - [MT7622_POWER_DOMAIN_HIF0] = { - .sta_mask = PWR_STATUS_HIF0, - .ctl_offs = SPM_HIF0_PWR_CON, - .sram_pdn_bits = GENMASK(11, 8), - .sram_pdn_ack_bits = GENMASK(15, 12), - .bus_prot_mask = GENMASK(25, 24), - }, - [MT7622_POWER_DOMAIN_HIF1] = { - .sta_mask = PWR_STATUS_HIF1, - .ctl_offs = SPM_HIF1_PWR_CON, - .sram_pdn_bits = GENMASK(11, 8), - .sram_pdn_ack_bits = GENMASK(15, 12), - .bus_prot_mask = GENMASK(28, 26), - }, -}; +#include "mtk-power-domain.h" /** * This function enables the bus protection bits for disabled power @@ -298,7 +158,7 @@ static int mtk_scpsys_power_off(struct power_domain *power_domain) return 0; } -static int mtk_power_domain_probe(struct udevice *dev) +int mtk_power_domain_probe(struct udevice *dev) { struct ofnode_phandle_args args; struct mtk_scp_domain *scpd = dev_get_priv(dev); @@ -335,32 +195,7 @@ static int mtk_power_domain_probe(struct udevice *dev) return clk_enable_bulk(&bulk); } -static const struct udevice_id mtk_power_domain_ids[] = { - { - .compatible = "mediatek,mt2701-scpsys", - .data = (ulong)&scp_domain_mt2701, - }, - { - .compatible = "mediatek,mt7622-scpsys", - .data = (ulong)&scp_domain_mt7622, - }, - { - .compatible = "mediatek,mt7623-scpsys", - .data = (ulong)&scp_domain_mt2701, - }, - { /* sentinel */ } -}; - -static const struct power_domain_ops mtk_power_domain_ops = { +const struct power_domain_ops mtk_power_domain_ops = { .off = mtk_scpsys_power_off, .on = mtk_scpsys_power_on, }; - -U_BOOT_DRIVER(mtk_power_domain) = { - .name = "mtk_power_domain", - .id = UCLASS_POWER_DOMAIN, - .ops = &mtk_power_domain_ops, - .probe = mtk_power_domain_probe, - .of_match = mtk_power_domain_ids, - .priv_auto = sizeof(struct mtk_scp_domain), -}; diff --git a/drivers/power/domain/mtk-power-domain.h b/drivers/power/domain/mtk-power-domain.h new file mode 100644 index 00000000000..0c2c06a045f --- /dev/null +++ b/drivers/power/domain/mtk-power-domain.h @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 MediaTek Inc. + * Copyright (C) 2026 BayLibre, SAS + * Author: Ryder Lee + * Julien Stephan + */ + +#ifndef __MTK_POWER_DOMAIN_H +#define __MTK_POWER_DOMAIN_H + +#include +#include +#include +#include + +struct udevice; + +#define SPM_EN (0xb16 << 16 | 0x1) +#define SPM_VDE_PWR_CON 0x0210 +#define SPM_MFG_PWR_CON 0x0214 +#define SPM_ISP_PWR_CON 0x0238 +#define SPM_DIS_PWR_CON 0x023c +#define SPM_CONN_PWR_CON 0x0280 +#define SPM_BDP_PWR_CON 0x029c +#define SPM_ETH_PWR_CON 0x02a0 +#define SPM_HIF_PWR_CON 0x02a4 +#define SPM_IFR_MSC_PWR_CON 0x02a8 +#define SPM_ETHSYS_PWR_CON 0x2e0 +#define SPM_HIF0_PWR_CON 0x2e4 +#define SPM_HIF1_PWR_CON 0x2e8 +#define SPM_PWR_STATUS 0x60c +#define SPM_PWR_STATUS_2ND 0x610 + +#define PWR_RST_B_BIT BIT(0) +#define PWR_ISO_BIT BIT(1) +#define PWR_ON_BIT BIT(2) +#define PWR_ON_2ND_BIT BIT(3) +#define PWR_CLK_DIS_BIT BIT(4) + +#define PWR_STATUS_CONN BIT(1) +#define PWR_STATUS_DISP BIT(3) +#define PWR_STATUS_MFG BIT(4) +#define PWR_STATUS_ISP BIT(5) +#define PWR_STATUS_VDEC BIT(7) +#define PWR_STATUS_BDP BIT(14) +#define PWR_STATUS_ETH BIT(15) +#define PWR_STATUS_HIF BIT(16) +#define PWR_STATUS_IFR_MSC BIT(17) +#define PWR_STATUS_ETHSYS BIT(24) +#define PWR_STATUS_HIF0 BIT(25) +#define PWR_STATUS_HIF1 BIT(26) + +/* Infrasys configuration */ +#define INFRA_TOPDCM_CTRL 0x10 +#define INFRA_TOPAXI_PROT_EN 0x220 +#define INFRA_TOPAXI_PROT_STA1 0x228 + +#define DCM_TOP_EN BIT(0) + +struct mtk_scp_domain; + +struct mtk_scp_domain_data { + u32 sta_mask; + int ctl_offs; + u32 sram_pdn_bits; + u32 sram_pdn_ack_bits; + u32 bus_prot_mask; +}; + +struct mtk_scp_domain { + void __iomem *base; + void __iomem *infracfg; + const struct mtk_scp_domain_data *data; +}; + +int mtk_power_domain_probe(struct udevice *dev); + +extern const struct power_domain_ops mtk_power_domain_ops; + +#endif /* __MTK_POWER_DOMAIN_H */