// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2026 NXP
 */

/ {
	binman {
		multiple-images;

		m33-oei-ddrfw {
			pad-byte = <0x00>;
			align-size = <0x8>;
			filename = "m33-oei-ddrfw.bin";

			oei-m33-ddr {
				align-size = <0x4>;
				filename = "oei-m33-ddr.bin";
				type = "blob-ext";
			};

			imx-lpddr {
				type = "nxp-header-ddrfw";

				imx-lpddr-imem {
					filename = "lpddr4x_imem_v202409.bin";
					type = "blob-ext";
				};

				imx-lpddr-dmem {
					filename = "lpddr4x_dmem_v202409.bin";
					type = "blob-ext";
				};
			};

			imx-lpddr-qb {
				type = "nxp-header-ddrfw";

				imx-lpddr-imem-qb {
					filename = "lpddr4x_imem_qb_v202409.bin";
					type = "blob-ext";
				};

				imx-lpddr-dmem-qb {
					filename = "lpddr4x_dmem_qb_v202409.bin";
					type = "blob-ext";
				};
			};
		};

		imx-boot {
			filename = "flash.bin";
			pad-byte = <0x00>;

			spl {
				type = "nxp-imx9image";
				cfg-path = "spl/u-boot-spl.cfgout";
				args;

				cntr-version = <2>;
				boot-from = "sd";
				soc-type = "IMX9";
				append = "mx952a0-ahab-container.img";
				container;
				dummy-ddr;
				image0 = "oei", "m33-oei-ddrfw.bin", "0x1ffc0000";
				hold = <0x10000>;
				image1 = "m33", "m33_image.bin", "0x1ffc0000";
				image2 = "a55", "spl/u-boot-spl.bin", "0x20480000";
				dummy-v2x = <0x8b000000>;
			};

			u-boot {
				type = "nxp-imx9image";
				cfg-path = "u-boot-container.cfgout";
				args;

				cntr-version = <2>;
				boot-from = "sd";
				soc-type = "IMX9";
				container;
				image0 = "a55", "bl31.bin", "0x8a200000";
				image1 = "a55", "u-boot.bin", "0x90200000";
			};
		};
	};

	chosen {
		bootargs = "console=ttyLP0,115200 earlycon";
	};
};

&A55_0 {
	clocks = <&scmi_clk IMX952_CLK_ARMPLL_PFD0>;
	/delete-property/ power-domains;
};

&A55_1 {
	clocks = <&scmi_clk IMX952_CLK_ARMPLL_PFD0>;
	/delete-property/ power-domains;
};

&A55_2 {
	clocks = <&scmi_clk IMX952_CLK_ARMPLL_PFD0>;
	/delete-property/ power-domains;
};

&A55_3 {
	clocks = <&scmi_clk IMX952_CLK_ARMPLL_PFD0>;
	/delete-property/ power-domains;
};

&aips1 {
	bootph-all;
};

&aips2 {
	bootph-all;

	wdog4: watchdog@420c0000 {
		compatible = "fsl,imx93-wdt";
		reg = <0x420c0000 0x10000>;
		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>;
		timeout-sec = <40>;
		status = "disabled";
		bootph-all;
	};
};

&aips3 {
	bootph-all;
};

&clk_ext1 {
	bootph-all;
};

&clk_dummy {
	bootph-all;
};

&clk_osc_24m {
	bootph-all;
};

&elemu1 {
	status = "okay";
	bootph-all;
};

&elemu3 {
	status = "okay";
	bootph-all;
};

&{/firmware} {
	bootph-all;
};

&{/firmware/scmi} {
	bootph-all;
};

&{/firmware/scmi/protocol@11} {
	bootph-all;
};

&{/firmware/scmi/protocol@13} {
	bootph-all;
};

&{/firmware/scmi/protocol@14} {
	bootph-all;
};

&{/firmware/scmi/protocol@15} {
	bootph-all;
};

&{/firmware/scmi/protocol@19} {
	bootph-all;
};

&gpio2 {
	bootph-pre-ram;
	/*
	 * Use one SPL/U-Boot for mx952evk and mx952evkrpmsg, since GPIO2
	 * is assigned to M7, disable gpio2 here
	 */
	status = "disabled";
};

&gpio3 {
	bootph-pre-ram;
};

&gpio4 {
	bootph-pre-ram;
};

&gpio5 {
	bootph-pre-ram;
};

&lpuart1 {
	bootph-pre-ram;
};

&mu2 {
	bootph-all;
};

&reg_usdhc2_vmmc {
	bootph-pre-ram;
};

&scmi_buf0 {
	reg = <0x0 0x400>;
	bootph-all;
};

&scmi_buf1 {
	bootph-all;
};

&{/soc} {
	bootph-all;
};

&sram0 {
	bootph-all;
};

&usdhc1 {
	bootph-pre-ram;
};

&usdhc2 {
	bootph-pre-ram;
};

&wdog3 {
	bootph-all;
};

&scmi_iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	pinctrl_hog: hoggrp {
		bootph-pre-ram;

		fsl,pins = <
			IMX952_PAD_XSPI1_SS1_B__WAKEUPMIX_TOP_GPIO5_IO_11	0x3fe
			IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_TPM3_CH2		0x51e
			IMX952_PAD_CCM_CLKO1__WAKEUPMIX_TOP_GPIO3_IO_26		0x3fe
			IMX952_PAD_CCM_CLKO2__WAKEUPMIX_TOP_GPIO3_IO_27		0x3fe
		>;
	};
};

&pinctrl_uart1 {
	bootph-pre-ram;
};

&pinctrl_usdhc1 {
	bootph-pre-ram;
};

&pinctrl_usdhc1_100mhz {
	bootph-pre-ram;
};

&pinctrl_usdhc1_200mhz {
	bootph-pre-ram;
};

&pinctrl_usdhc2 {
	bootph-pre-ram;
};

&pinctrl_usdhc2_100mhz {
	bootph-pre-ram;
};

&pinctrl_usdhc2_200mhz {
	bootph-pre-ram;
};

&pinctrl_usdhc2_gpio {
	bootph-pre-ram;
};

&pinctrl_reg_usdhc2_vmmc {
	bootph-pre-ram;
};
