// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Toradex Verdin AM62 dts file for R5 SPL
 * Copyright 2023 Toradex - https://www.toradex.com/
 */

#include "k3-am625-verdin-wifi-dev.dts"
#include "k3-am625-verdin-lpddr4-1600MTs.dtsi"
#include "k3-am62-ddr.dtsi"

#include "k3-am625-verdin-wifi-dev-u-boot.dtsi"
#include "k3-am625-r5.dtsi"

/ {
	aliases {
		serial0 = &main_uart1;
		serial1 = &wkup_uart0;
		serial2 = &main_uart0;
		serial3 = &mcu_uart0;
		serial4 = &main_uart5;
		remoteproc0 = &sysctrler;
		remoteproc1 = &a53_0;
	};
};

&a53_0 {
	/*
	 * FIXME: Currently only the SPL running on the R5 has a clock
	 * driver. As a workaround therefore move the assigned-clock
	 * stuff required for our ETH_25MHz_CLK from the cpsw3g_mdio
	 * node of the regular device tree to here (last one each in
	 * below three lines, adding a <0> as spacing for parents).
	 */
	assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>, <&k3_clks 157 20>;
	assigned-clock-parents = <&k3_clks 61 2>, <0>, <&k3_clks 157 22>;
	assigned-clock-rates = <200000000>, <800000000>, <25000000>;
};
