/* SPDX-License-Identifier: GPL-2.0+ */
#ifndef	_OMAP_CLOCK_H_
#define	_OMAP_CLOCK_H_

/* CM_CLKMODE_DPLL */
#define CM_CLKMODE_DPLL_EN_SHIFT	0
#define CM_CLKMODE_DPLL_EN_MASK		(0x7 << 0)

#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT	0
#define CM_CLKMODE_DPLL_DPLL_EN_MASK	7

#define DPLL_EN_STOP			1
#define DPLL_EN_MN_BYPASS		4
#define DPLL_EN_LOW_POWER_BYPASS	5
#define DPLL_EN_FAST_RELOCK_BYPASS	6
#define DPLL_EN_LOCK			7

#define DPLL_NO_LOCK		0
#define DPLL_LOCK		1

/* CM_IDLEST_DPLL fields */
#define ST_DPLL_CLK_MASK	1

/* CM_CLKSEL_CORE */
#define CLKSEL_CORE_SHIFT	0
#define CLKSEL_L3_SHIFT		4
#define CLKSEL_L4_SHIFT		8

/* CM_DLL_CTRL */
#define CM_DLL_CTRL_NO_OVERRIDE		0

/* CM_CLKSEL_DPLL */
#define CM_CLKSEL_DPLL_N_SHIFT		0
#define CM_CLKSEL_DPLL_N_MASK		0x7F
#define CM_CLKSEL_DPLL_M_SHIFT		8
#define CM_CLKSEL_DPLL_M_MASK		(0x7FF << 8)
#define CM_CLKSEL_DCC_EN_SHIFT		22
#define CM_CLKSEL_DCC_EN_MASK		BIT(22)

#define CLKSEL_CORE_X2_DIV_1	0
#define CLKSEL_L3_CORE_DIV_2	1
#define CLKSEL_L4_L3_DIV_2	1

/* CM_SYS_CLKSEL */
#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK		7

/*CM_<clock_domain>__CLKCTRL */
#define CD_CLKCTRL_CLKTRCTRL_SHIFT	0
#define CD_CLKCTRL_CLKTRCTRL_MASK	3

#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP	0
#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP	1
#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP	2
#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO	3

/* CM_SHADOW_FREQ_CONFIG1 */
#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK	1
#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK	4
#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK	8

#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT	8
#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK	(7 << 8)

#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT	11
#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK		(0x1F << 11)

/* CM_<clock_domain>_<module>_CLKCTRL */
#define MODULE_CLKCTRL_MODULEMODE_SHIFT		0
#define MODULE_CLKCTRL_MODULEMODE_MASK		3
#define MODULE_CLKCTRL_IDLEST_SHIFT		16
#define MODULE_CLKCTRL_IDLEST_MASK		(3 << 16)

#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE		0
#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO		1
#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN	2

#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL		0
#define MODULE_CLKCTRL_IDLEST_TRANSITIONING		1
#define MODULE_CLKCTRL_IDLEST_IDLE			2
#define MODULE_CLKCTRL_IDLEST_DISABLED			3

/* CM_L4PER_GPIO4_CLKCTRL */
#define GPIO4_CLKCTRL_OPTFCLKEN_MASK	BIT(8)

/* CM_WKUP_GPTIMER1_CLKCTRL */
#define GPTIMER1_CLKCTRL_CLKSEL_MASK	BIT(24)

/* CM_L3INIT_HSMMCn_CLKCTRL */
#define HSMMC_CLKCTRL_CLKSEL_MASK	BIT(24)
#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK	(3 << 25)

/* Clock frequencies */
#define OMAP_SYS_CLK_IND_38_4_MHZ	6

/* AUXCLKx reg fields */
#define AUXCLK_ENABLE_MASK		BIT(8)
#define AUXCLK_SRCSELECT_SHIFT		1
#define AUXCLK_SRCSELECT_MASK		(3 << 1)
#define AUXCLK_CLKDIV_SHIFT		16
#define AUXCLK_CLKDIV_MASK		(0xF << 16)
#define AUXCLK_CLKDIV_2			1

#define AUXCLK_SRCSELECT_SYS_CLK	0
#define AUXCLK_SRCSELECT_CORE_DPLL	1
#define AUXCLK_SRCSELECT_PER_DPLL	2
#define AUXCLK_SRCSELECT_ALTERNATE	3

/* CM_MPU_MPU_CLKCTRL */
#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT	24
#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK	(3 << 24)
#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT	26
#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK	BIT(26)

#endif /* _OMAP_CLOCK_H_ */
