#define CFG_SYS_HRCW_LOW (\
	(CONFIG_LBMC_CLOCK_MODE << (31 - 0)) |\
	(CONFIG_DDR_MC_CLOCK_MODE << (31 - 1)) |\
	(CONFIG_SYSTEM_PLL_VCO_DIV << (31 - 3)) |\
	(CONFIG_SYSTEM_PLL_FACTOR << (31 - 7)) |\
	(CONFIG_CORE_PLL_RATIO << (31 - 15)) |\
	(CONFIG_QUICC_VCO_DIVIDER << (31 - 25)) |\
	(CONFIG_QUICC_DIV_FACTOR << (31 - 26)) |\
	(CONFIG_QUICC_MULT_FACTOR << (31 - 31)) \
	)

#define CFG_SYS_HRCW_HIGH (\
	(CONFIG_PCI_HOST_MODE << (31 - 0)) |\
	(CONFIG_PCI_64BIT_MODE << (31 - 1)) |\
	(CONFIG_PCI_INT_ARBITER1 << (31 - 2)) |\
	(CONFIG_PCI_INT_ARBITER2 << (31 - 3)) |\
	(CONFIG_PCI_CLOCK_OUTPUT_DRIVE << (31 - 3)) |\
	(CONFIG_CORE_DISABLE_MODE << (31 - 4)) |\
	(CONFIG_BOOT_MEMORY_SPACE << (31 - 5)) |\
	(CONFIG_BOOT_SEQUENCER << (31 - 7)) |\
	(CONFIG_SOFTWARE_WATCHDOG << (31 - 8)) |\
	(CONFIG_BOOT_ROM_INTERFACE << (31 - 13)) |\
	(CONFIG_TSEC1_MODE << (31 - 18)) |\
	(CONFIG_TSEC2_MODE << (31 - 21)) |\
	(CONFIG_SECONDARY_DDR_IO << (31 - 27)) |\
	(CONFIG_TRUE_LITTLE_ENDIAN << (31 - 28)) |\
	(CONFIG_LALE_TIMING << (31 - 29)) |\
	(CONFIG_LDP_PIN_MUX_STATE << (31 - 30)) \
	)
