// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
 * Copyright (C) 2026 RISCstar Ltd.
 */

#include "binman.dtsi"

/ {
	memory@0 {
		device_type = "memory";
		reg = <0x00000000 0x00000000 0x00000000 0x80000000>;
	};
};

&uart0 {
	bootph-pre-ram;
};

&osc_32k {
	bootph-pre-ram;
};

&vctcxo_1m {
	bootph-pre-ram;
};

&vctcxo_3m {
	bootph-pre-ram;
};

&vctcxo_24m {
	bootph-pre-ram;
};

&syscon_mpmu {
	bootph-pre-ram;
};

&pll {
	bootph-pre-ram;
};

&syscon_apmu {
	bootph-pre-ram;
};

&syscon_apbc {
	bootph-pre-ram;
};

&i2c2 {
	bootph-pre-ram;
	resets = <&syscon_apbc RESET_TWSI2>;

	eeprom@50 {
		bootph-pre-ram;
	};
};

/*
 * The kernel pmic@41 nodes use the standard regulator-* properties only;
 * U-Boot's regulator framework looks up suppliers by `regulator-name`.
 * Carry the U-Boot-specific names (vdd_core / vdd_1v8 / vdd_1v8_mmc) here
 * so SPL can program the bucks that DDR training depends on.
 */
&i2c8 {
	bootph-pre-ram;
	resets = <&syscon_apbc RESET_TWSI8>;

	pmic@41 {
		bootph-pre-ram;

		regulators {
			buck1 {
				regulator-name = "vdd_core";
				bootph-pre-ram;
			};

			buck3 {
				regulator-name = "vdd_1v8";
				bootph-pre-ram;
			};

			aldo1 {
				regulator-name = "vdd_1v8_mmc";
				bootph-pre-ram;
			};
		};
	};
};

&binman {
	u-boot-spl-ddr {
		type = "section";
		filename = "u-boot-spl-ddr.bin";
		pad-byte = <0xff>;

		u-boot-spl {
		};

		ddr-fw {
			type = "blob";
			filename = "ddr_fw.bin";
			align = <64>;
		};

		u-boot-any {
			type = "section";
			size = <0>;
			offset = <0>;
		};
	};
};
