// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * phyCORE-AM62Ax dts file for R5 SPL
 * Copyright (C) 2024 PHYTEC America LLC
 * Author: Garrett Giordano <ggiordano@phytec.com>
 *
 * Product homepage:
 * https://www.phytec.com/product/phycore-am62ax
 */

#include "k3-am62a7-phyboard-lyra-rdk.dts"
#include "k3-am62a-phycore-som-ddr4-2gb.dtsi"
#include "k3-am62a-ddr.dtsi"

#include "k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi"
#include "k3-am62a7-r5.dtsi"

/ {
	aliases {
		serial0 = &wkup_uart0;
		serial3 = &main_uart1;
	};
};

&cbass_main {
	bootph-pre-ram;
	sa3_secproxy: secproxy@44880000 {
		compatible = "ti,am654-secure-proxy";
		#mbox-cells = <1>;
		reg = <0x00 0x44880000 0x00 0x20000>,
		      <0x0 0x44860000 0x0 0x20000>,
		      <0x0 0x43600000 0x0 0x10000>;
		reg-names = "rt", "scfg", "target_data";
		bootph-pre-ram;
	};

	sysctrler: sysctrler {
		compatible = "ti,am654-tisci-rproc-r5";
		mboxes= <&secure_proxy_main 1>,
			<&secure_proxy_main 0>,
			<&sa3_secproxy 0>;
		mbox-names = "tx", "rx", "boot_notify";
		bootph-pre-ram;
	};
};

&main_bcdma {
	ti,sci = <&dm_tifs>;
};

&main_pktdma {
	ti,sci = <&dm_tifs>;
};

&main_pmx0 {
	bootph-pre-ram;
};

/* Main UART1 is used for TIFS firmware logs */
&main_uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_uart1_pins_default>;
	status = "okay";
	bootph-pre-ram;
};

&mcu_pmx0 {
	status = "okay";
	bootph-pre-ram;

	wkup_uart0_pins_default: wkup-uart0-pins-default {
		pinctrl-single,pins = <
			AM62X_MCU_IOPAD(0x02c, PIN_INPUT, 0)	/* (C6) WKUP_UART0_CTSn */
			AM62X_MCU_IOPAD(0x030, PIN_OUTPUT, 0)	/* (A4) WKUP_UART0_RTSn */
			AM62X_MCU_IOPAD(0x024, PIN_INPUT, 0)	/* (B4) WKUP_UART0_RXD */
			AM62X_MCU_IOPAD(0x028, PIN_OUTPUT, 0)	/* (C5) WKUP_UART0_TXD */
		>;
		bootph-pre-ram;
	};
};

&ospi0 {
	reg = <0x00 0x0fc40000 0x00 0x100>,
	      <0x00 0x60000000 0x00 0x08000000>;
};

/* WKUP UART0 is used for DM firmware logs */
&wkup_uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&wkup_uart0_pins_default>;
	status = "okay";
	bootph-pre-ram;
};
