// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

#include "rockchip-u-boot.dtsi"

/ {
	aliases {
		mmc0 = &sdhci;
		mmc1 = &sdmmc;
	};

	chosen {
		u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
	};

	dmc {
		compatible = "rockchip,rk3528-dmc";
		bootph-all;
	};

	soc {
		rng: rng@ffc50000 {
			compatible = "rockchip,rkrng";
			reg = <0x0 0xffc50000 0x0 0x200>;
		};

		otp: efuse@ffce0000 {
			compatible = "rockchip,rk3528-otp";
			reg = <0x0 0xffce0000 0x0 0x4000>;
		};
	};
};

&cru {
	bootph-all;
};

&emmc_bus8 {
	bootph-pre-ram;
	bootph-some-ram;
};

&emmc_clk {
	bootph-pre-ram;
	bootph-some-ram;
};

&emmc_cmd {
	bootph-pre-ram;
	bootph-some-ram;
};

&emmc_strb {
	bootph-pre-ram;
	bootph-some-ram;
};

&gmac0_clk {
	bootph-all;
};

&ioc_grf {
	bootph-all;
};

&otp {
	bootph-some-ram;
};

&pcfg_pull_none {
	bootph-all;
};

&pcfg_pull_up {
	bootph-all;
};

&pcfg_pull_up_drv_level_2 {
	bootph-pre-ram;
	bootph-some-ram;
};

&pinctrl {
	bootph-all;
};

&sdhci {
	bootph-pre-ram;
	bootph-some-ram;
	u-boot,spl-fifo-mode;
};

&sdmmc {
	bootph-pre-ram;
	bootph-some-ram;
	u-boot,spl-fifo-mode;
};

&sdmmc_bus4 {
	bootph-pre-ram;
	bootph-some-ram;
};

&sdmmc_clk {
	bootph-pre-ram;
	bootph-some-ram;
};

&sdmmc_cmd {
	bootph-pre-ram;
	bootph-some-ram;
};

&sdmmc_det {
	bootph-pre-ram;
	bootph-some-ram;
};

&uart0 {
	bootph-all;
	clock-frequency = <24000000>;
};

&uart0m0_xfer {
	bootph-pre-sram;
	bootph-pre-ram;
};

&xin24m {
	bootph-all;
};
