// SPDX-License-Identifier: GPL-2.0
/*
 * dts file for AMD MicroBlaze V
 *
 * (C) Copyright 2023 - 2025, Advanced Micro Devices, Inc.
 *
 * Michal Simek <michal.simek@amd.com>
 */

/dts-v1/;

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	model = "AMD MicroBlaze V 32bit";
	compatible = "qemu,mbv", "amd,mbv";

	cpus: cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		timebase-frequency = <100000000>;
		cpu_0: cpu@0 {
			compatible = "amd,mbv32", "riscv";
			device_type = "cpu";
			reg = <0>;
			riscv,isa = "rv32imafdc";
			mmu-type = "riscv,sv39";
			i-cache-size = <32768>;
			d-cache-size = <32768>;
			clock-frequency = <100000000>;
			cpu0_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};
	};

	aliases {
		serial0 = &uart0;
	};

	chosen {
		bootargs = "earlycon";
		stdout-path = "serial0:115200n8";
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x40000000>;
	};

	clk100: clock {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
	};

	axi: axi {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges;
		bootph-all;

		axi_intc: interrupt-controller@41200000 {
			compatible = "xlnx,xps-intc-1.00.a";
			reg = <0x41200000 0x1000>;
			interrupt-controller;
			interrupt-parent = <&cpu0_intc>;
			#interrupt-cells = <2>;
			xlnx,num-intr-inputs = <2>;
			xlnx,kind-of-intr = <0>;
		};

		xlnx_timer0: timer@41c00000 {
			compatible = "xlnx,xps-timer-1.00.a";
			reg = <0x41c00000 0x1000>;
			interrupt-parent = <&axi_intc>;
			interrupts = <0 2>;
			bootph-all;
			xlnx,one-timer-only = <0>;
			clock-names = "s_axi_aclk";
			clocks = <&clk100>;
		};

		uart0: serial@40600000 {
			compatible = "xlnx,xps-uartlite-1.00.a";
			reg = <0x40600000 0x1000>;
			interrupt-parent = <&axi_intc>;
			interrupts = <1 2>;
			bootph-all;
			clocks = <&clk100>;
			current-speed = <115200>;
			xlnx,data-bits = <8>;
			xlnx,use-parity = <0>;
		};
	};
};
