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Use $CC in makefile

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master
vhaudiquet 1 year ago
parent bbe2b8ba05
commit ee7d957ba3
1 changed files with 1 additions and 1 deletions
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  1. 2
      Makefile

2
Makefile
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@ -13,7 +13,7 @@ all: resources $(BUILD_DIR)/$(NAME) $(BUILD_DIR)/drivers
resources: $(BUILD_DIR)/glib-2.0/schemas/gschemas.compiled resources: $(BUILD_DIR)/glib-2.0/schemas/gschemas.compiled
$(BUILD_DIR)/$(NAME): $(BUILD_DIR)/resource.c $(C_FILES) | $(BUILD_DIR) $(BUILD_DIR)/$(NAME): $(BUILD_DIR)/resource.c $(C_FILES) | $(BUILD_DIR)
gcc $(CFLAGS) -o $@ $^ $(LDFLAGS) $(CC) $(CFLAGS) -o $@ $^ $(LDFLAGS)
# Build directory # Build directory
$(BUILD_DIR): $(BUILD_DIR):

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